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Searched refs:VPTR (Results 1 – 23 of 23) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
D32-bit-local-address-space.ll25 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
26 ; SI: ds_read_b32 [[VPTR]]
36 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}}
37 ; SI: ds_read_b32 v{{[0-9]+}}, [[VPTR]] offset:4
49 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
50 ; SI: ds_read_b32 [[VPTR]]
121 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}}
123 ; SI: ds_write_b32 [[VPTR]], [[VAL]] offset:4
133 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
134 ; SI: ds_write_b32 [[VPTR]], v{{[0-9]+$}}
Datomic_cmp_swap_local.ll15 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
17 ; GCN: ds_cmpst_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[VCMP]], [[VSWAP]] offset:16
37 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
40 ; GCN: ds_cmpst_rtn_b64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}…
77 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
79 ; GCN: ds_cmpst_b32 [[VPTR]], [[VCMP]], [[VSWAP]] offset:16
98 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
101 ; GCN: ds_cmpst_b64 [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\…
Dds_write2st64.ll11 ; GCN-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
12 ; GCN: ds_write2st64_b32 [[VPTR]], [[VAL]], [[VAL]] offset1:1
37 ; GCN-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
38 ; GCN: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:2 offset1:5
66 ; GCN: v_add_{{i|u}}32_e32 [[VPTR:v[0-9]+]], {{(vcc, )?}}s{{[0-9]+}}, [[SHL]]
67 ; GCN: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:255
94 ; GCN: v_add_{{i|u}}32_e32 [[VPTR:v[0-9]+]], {{(vcc, )?}}s{{[0-9]+}}, [[SHL]]
95 ; GCN: ds_write2st64_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:4 offset1:127
Dds_write2.ll12 ; GCN-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
13 ; GCN: ds_write2_b32 [[VPTR]], [[VAL]], [[VAL]] offset1:8
37 ; GCN-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
38 ; GCN: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:8
106 ; GCN-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
111 ; GCN: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8
134 ; GCN-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
135 ; GCN: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8
156 ; GCN-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
157 ; GCN: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8
[all …]
Daddrspacecast.ll15 ; CI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
16 ; CI-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]]
27 ; GFX9-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
28 ; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]]
56 ; CI-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
57 ; CI-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]]
69 ; GFX9: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
70 ; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]]
Dlocal-atomics.ll15 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
16 ; GCN: ds_wrxchg_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]]
48 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
49 ; GCN: ds_add_rtn_u32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]]
401 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
402 ; GCN: ds_wrxchg_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]]
427 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
428 ; GCN: ds_add_u32 [[VPTR]], [[DATA]]
Dlocal-atomics64.ll50 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
51 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}…
367 ; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
Dllvm.amdgcn.atomic.inc.ll46 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
47 ; GCN: ds_inc_u32 [[VPTR]], [[DATA]]
Dllvm.amdgcn.atomic.dec.ll74 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
75 ; GCN: ds_dec_u32 [[VPTR]], [[DATA]]
Dds_read2.ll358 ; GCN-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 3, {{v[0-9]+}}
359 ; GCN: ds_read2_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, [[VPTR]] offset1:8
/external/llvm/test/CodeGen/AMDGPU/
D32-bit-local-address-space.ll25 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
26 ; SI: ds_read_b32 [[VPTR]]
36 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}}
37 ; SI: ds_read_b32 v{{[0-9]+}}, [[VPTR]] offset:4
49 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
50 ; SI: ds_read_b32 [[VPTR]]
121 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}}
123 ; SI: ds_write_b32 [[VPTR]], [[VAL]] offset:4
133 ; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
134 ; SI: ds_write_b32 [[VPTR]], v{{[0-9]+$}}
Datomic_cmp_swap_local.ll11 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
13 ; GCN: ds_cmpst_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[VCMP]], [[VSWAP]] offset:16
30 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
33 ; GCN: ds_cmpst_rtn_b64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}…
64 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
66 ; GCN: ds_cmpst_b32 [[VPTR]], [[VCMP]], [[VSWAP]] offset:16
82 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
85 ; GCN: ds_cmpst_b64 [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\…
Dds_write2st64.ll7 ; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
8 ; SI: ds_write2st64_b32 [[VPTR]], [[VAL]], [[VAL]] offset1:1
25 ; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
26 ; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:2 offset1:5
46 ; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
47 ; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:255
66 ; SI-DAG: v_add_i32_e32 [[VPTR:v[0-9]+]],
67 ; SI: ds_write2st64_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:4 offset1:127
Dds_write2.ll9 ; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
10 ; SI: ds_write2_b32 [[VPTR]], [[VAL]], [[VAL]] offset1:8
27 ; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
28 ; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:8
86 ; SI: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
87 ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8
107 ; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
108 ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8
126 ; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
127 ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8
[all …]
Dlocal-atomics64.ll37 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
38 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}…
51 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}
92 ; GCN: ds_sub_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}
282 ; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
283 ; GCN: ds_add_u64 [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} offset:32
294 ; GCN: ds_add_u64 [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}
330 ; GCN: ds_sub_u64 [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}
Dlocal-atomics.ll10 ; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
11 ; GCN: ds_wrxchg_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]]
36 ; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
37 ; GCN: ds_add_rtn_u32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]]
310 ; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
311 ; GCN: ds_wrxchg_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]]
330 ; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
331 ; GCN: ds_add_u32 [[VPTR]], [[DATA]]
Daddrspacecast.ll12 ; HSA-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
16 ; HSA-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]]
35 ; HSA-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
39 ; HSA-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]]
Dllvm.amdgcn.atomic.inc.ll36 ; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
37 ; GCN: ds_inc_u32 [[VPTR]], [[DATA]]
Dllvm.amdgcn.atomic.dec.ll36 ; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
37 ; GCN: ds_dec_u32 [[VPTR]], [[DATA]]
Dds_read2.ll313 ; SI: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 3, {{v[0-9]+}}
314 ; SI: ds_read2_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, [[VPTR]] offset1:8
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/llvm-ir/
Dextractelement.ll17 ; ALL-DAG: addiu [[VPTR:\$[0-9]+]], $sp, 6
18 ; ALL-DAG: or [[EPTR:\$[0-9]+]], [[VPTR]], [[MASKED_IDX]]
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dextractelement.ll17 ; ALL-DAG: addiu [[VPTR:\$[0-9]+]], $sp, 6
18 ; ALL-DAG: addu [[EPTR:\$[0-9]+]], $4, [[VPTR]]
/external/clang/lib/CodeGen/
DCGDebugInfo.cpp1551 llvm::DIType *VPTR = DBuilder.createMemberType( in CollectVTableInfo() local
1554 EltTys.push_back(VPTR); in CollectVTableInfo()