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Searched refs:VectorFormat (Results 1 – 21 of 21) sorted by relevance

/external/v8/src/codegen/arm64/
Dregister-arm64.cc12 VectorFormat VectorFormatHalfWidth(VectorFormat vform) { in VectorFormatHalfWidth()
33 VectorFormat VectorFormatDoubleWidth(VectorFormat vform) { in VectorFormatDoubleWidth()
54 VectorFormat VectorFormatFillQ(VectorFormat vform) { in VectorFormatFillQ()
77 VectorFormat VectorFormatHalfWidthDoubleLanes(VectorFormat vform) { in VectorFormatHalfWidthDoubleLanes()
96 VectorFormat VectorFormatDoubleLanes(VectorFormat vform) { in VectorFormatDoubleLanes()
110 VectorFormat VectorFormatHalfLanes(VectorFormat vform) { in VectorFormatHalfLanes()
124 VectorFormat ScalarFormatFromLaneSize(int laneSize) { in ScalarFormatFromLaneSize()
139 VectorFormat VectorFormatFillQ(int laneSize) { in VectorFormatFillQ()
143 VectorFormat ScalarFormatFromFormat(VectorFormat vform) { in ScalarFormatFromFormat()
147 unsigned RegisterSizeInBytesFromFormat(VectorFormat vform) { in RegisterSizeInBytesFromFormat()
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Dregister-arm64.h256 enum VectorFormat { enum
278 VectorFormat VectorFormatHalfWidth(VectorFormat vform);
279 VectorFormat VectorFormatDoubleWidth(VectorFormat vform);
280 VectorFormat VectorFormatDoubleLanes(VectorFormat vform);
281 VectorFormat VectorFormatHalfLanes(VectorFormat vform);
282 VectorFormat ScalarFormatFromLaneSize(int lanesize);
283 VectorFormat VectorFormatHalfWidthDoubleLanes(VectorFormat vform);
284 VectorFormat VectorFormatFillQ(int laneSize);
285 VectorFormat VectorFormatFillQ(VectorFormat vform);
286 VectorFormat ScalarFormatFromFormat(VectorFormat vform);
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Dinstructions-arm64.cc383 VectorFormat NEONFormatDecoder::GetVectorFormat(int format_index) { in GetVectorFormat()
387 VectorFormat NEONFormatDecoder::GetVectorFormat( in GetVectorFormat()
389 static const VectorFormat vform[] = { in GetVectorFormat()
Dinstructions-arm64.h628 VectorFormat GetVectorFormat(int format_index = 0);
629 VectorFormat GetVectorFormat(const NEONFormatMap* format_map);
Dassembler-arm64.cc1888 (vd_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in ins()
1918 (vn_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in smov()
2076 (vn_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in umov()
2116 (vd_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in ins()
2118 (vn_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in ins()
Dassembler-arm64.h2309 int s = LaneSizeInBytesLog2FromFormat(static_cast<VectorFormat>(format)); in ImmNEON5()
2316 int s = LaneSizeInBytesLog2FromFormat(static_cast<VectorFormat>(format)); in ImmNEON4()
Dmacro-assembler-arm64.h2095 VRegister AcquireV(VectorFormat format) { in AcquireV()
/external/v8/src/execution/arm64/
Dsimulator-arm64.h388 int64_t Int(VectorFormat vform, int index) const { in Int()
410 uint64_t Uint(VectorFormat vform, int index) const { in Uint()
432 uint64_t UintLeftJustified(VectorFormat vform, int index) const { in UintLeftJustified()
436 int64_t IntLeftJustified(VectorFormat vform, int index) const { in IntLeftJustified()
443 void SetInt(VectorFormat vform, int index, int64_t value) const { in SetInt()
463 void SetIntArray(VectorFormat vform, const int64_t* src) const { in SetIntArray()
470 void SetUint(VectorFormat vform, int index, uint64_t value) const { in SetUint()
490 void SetUintArray(VectorFormat vform, const uint64_t* src) const { in SetUintArray()
497 void ReadUintFromMem(VectorFormat vform, int index, uint64_t addr) const;
499 void WriteUintToMem(VectorFormat vform, int index, uint64_t addr) const;
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Dsimulator-logic-arm64.cc346 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1()
354 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, int index, in ld1()
359 void Simulator::ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1r()
366 void Simulator::ld2(VectorFormat vform, LogicVRegister dst1, in ld2()
380 void Simulator::ld2(VectorFormat vform, LogicVRegister dst1, in ld2()
389 void Simulator::ld2r(VectorFormat vform, LogicVRegister dst1, in ld2r()
400 void Simulator::ld3(VectorFormat vform, LogicVRegister dst1, in ld3()
418 void Simulator::ld3(VectorFormat vform, LogicVRegister dst1, in ld3()
431 void Simulator::ld3r(VectorFormat vform, LogicVRegister dst1, in ld3r()
445 void Simulator::ld4(VectorFormat vform, LogicVRegister dst1, in ld4()
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Dsimulator-arm64.cc784 void LogicVRegister::ReadUintFromMem(VectorFormat vform, int index, in ReadUintFromMem()
804 void LogicVRegister::WriteUintToMem(VectorFormat vform, int index, in WriteUintToMem()
1047 VectorFormat vform) { in GetPrintRegisterFormat()
1080 VectorFormat vform) { in GetPrintRegisterFormatFP()
2926 VectorFormat vform = (instr->Mask(FP64) == FP64) ? kFormatD : kFormatS; in VisitFPDataProcessing1Source()
3017 VectorFormat vform = (instr->Mask(FP64) == FP64) ? kFormatD : kFormatS; in VisitFPDataProcessing2Source()
3682 VectorFormat vf = nfd.GetVectorFormat(); in VisitNEON2RegMisc()
3687 VectorFormat vf_lp = nfd.GetVectorFormat(&map_lp); in VisitNEON2RegMisc()
3690 VectorFormat vf_fcvtl = nfd.GetVectorFormat(&map_fcvtl); in VisitNEON2RegMisc()
3694 VectorFormat vf_fcvtn = nfd.GetVectorFormat(&map_fcvtn); in VisitNEON2RegMisc()
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/external/vixl/src/aarch64/
Dsimulator-aarch64.h207 int64_t Int(VectorFormat vform, int index) const { in Int()
229 uint64_t Uint(VectorFormat vform, int index) const { in Uint()
251 uint64_t UintLeftJustified(VectorFormat vform, int index) const { in UintLeftJustified()
255 int64_t IntLeftJustified(VectorFormat vform, int index) const { in IntLeftJustified()
262 void SetInt(VectorFormat vform, int index, int64_t value) const { in SetInt()
282 void SetIntArray(VectorFormat vform, const int64_t* src) const { in SetIntArray()
289 void SetUint(VectorFormat vform, int index, uint64_t value) const { in SetUint()
309 void SetUintArray(VectorFormat vform, const uint64_t* src) const { in SetUintArray()
316 void ReadUintFromMem(VectorFormat vform, int index, uint64_t addr) const { in ReadUintFromMem()
336 void WriteUintToMem(VectorFormat vform, int index, uint64_t addr) const { in WriteUintToMem()
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Dlogic-aarch64.cc170 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1()
179 void Simulator::ld1(VectorFormat vform, in ld1()
187 void Simulator::ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1r()
195 void Simulator::ld2(VectorFormat vform, in ld2()
212 void Simulator::ld2(VectorFormat vform, in ld2()
225 void Simulator::ld2r(VectorFormat vform, in ld2r()
239 void Simulator::ld3(VectorFormat vform, in ld3()
261 void Simulator::ld3(VectorFormat vform, in ld3()
278 void Simulator::ld3r(VectorFormat vform, in ld3r()
296 void Simulator::ld4(VectorFormat vform, in ld4()
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Dinstructions-aarch64.cc399 VectorFormat VectorFormatHalfWidth(VectorFormat vform) { in VectorFormatHalfWidth()
422 VectorFormat VectorFormatDoubleWidth(VectorFormat vform) { in VectorFormatDoubleWidth()
445 VectorFormat VectorFormatFillQ(VectorFormat vform) { in VectorFormatFillQ()
469 VectorFormat VectorFormatHalfWidthDoubleLanes(VectorFormat vform) { in VectorFormatHalfWidthDoubleLanes()
489 VectorFormat VectorFormatDoubleLanes(VectorFormat vform) { in VectorFormatDoubleLanes()
505 VectorFormat VectorFormatHalfLanes(VectorFormat vform) { in VectorFormatHalfLanes()
521 VectorFormat ScalarFormatFromLaneSize(int laneSize) { in ScalarFormatFromLaneSize()
538 VectorFormat ScalarFormatFromFormat(VectorFormat vform) { in ScalarFormatFromFormat()
543 unsigned RegisterSizeInBitsFromFormat(VectorFormat vform) { in RegisterSizeInBitsFromFormat()
566 unsigned RegisterSizeInBytesFromFormat(VectorFormat vform) { in RegisterSizeInBytesFromFormat()
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Dinstructions-aarch64.h570 enum VectorFormat { enum
598 VectorFormat VectorFormatHalfWidth(VectorFormat vform);
599 VectorFormat VectorFormatDoubleWidth(VectorFormat vform);
600 VectorFormat VectorFormatDoubleLanes(VectorFormat vform);
601 VectorFormat VectorFormatHalfLanes(VectorFormat vform);
602 VectorFormat ScalarFormatFromLaneSize(int lanesize);
603 VectorFormat VectorFormatHalfWidthDoubleLanes(VectorFormat vform);
604 VectorFormat VectorFormatFillQ(VectorFormat vform);
605 VectorFormat ScalarFormatFromFormat(VectorFormat vform);
606 unsigned RegisterSizeInBitsFromFormat(VectorFormat vform);
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Dsimulator-aarch64.cc565 VectorFormat vform) { in GetPrintRegisterFormat()
600 VectorFormat vform) { in GetPrintRegisterFormatFP()
3498 VectorFormat vform; in VisitFPDataProcessing1Source()
3644 VectorFormat vform; in VisitFPDataProcessing2Source()
4085 VectorFormat vf = nfd.GetVectorFormat(); in VisitNEON2RegMisc()
4089 VectorFormat vf_lp = nfd.GetVectorFormat(&map_lp); in VisitNEON2RegMisc()
4092 VectorFormat vf_fcvtl = nfd.GetVectorFormat(&map_fcvtl); in VisitNEON2RegMisc()
4096 VectorFormat vf_fcvtn = nfd.GetVectorFormat(&map_fcvtn); in VisitNEON2RegMisc()
4183 VectorFormat fpf = nfd.GetVectorFormat(nfd.FPFormatMap()); in VisitNEON2RegMisc()
4367 VectorFormat fpf = nfd.GetVectorFormat(&map_half); in VisitNEON2RegMiscFP16()
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Doperands-aarch64.h320 VRegister(unsigned code, VectorFormat format) in VRegister()
Dassembler-aarch64.cc4482 (vd_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in ins()
4485 (vn_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in ins()
4528 (vd_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in ins()
4569 (vn_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in umov()
4605 (vn_index < LaneCountFromFormat(static_cast<VectorFormat>(format)))); in smov()
Dassembler-aarch64.h4172 int s = LaneSizeInBytesLog2FromFormat(static_cast<VectorFormat>(format)); in ImmNEON5()
4179 int s = LaneSizeInBytesLog2FromFormat(static_cast<VectorFormat>(format)); in ImmNEON4()
/external/v8/src/compiler/backend/arm64/
Dcode-generator-arm64.cc424 Arm64OperandConverter i, VectorFormat scalar, in EmitFpOrNeonUnop()
425 VectorFormat vector) { in EmitFpOrNeonUnop()
426 VectorFormat f = instr->InputAt(0)->IsSimd128Register() ? vector : scalar; in EmitFpOrNeonUnop()
1143 VectorFormat dst_f = VectorFormatFillQ(MiscField::decode(opcode)); in AssembleArchInstruction()
1144 VectorFormat src_f = VectorFormatHalfWidthDoubleLanes(dst_f); in AssembleArchInstruction()
1150 VectorFormat dst_f = VectorFormatFillQ(MiscField::decode(opcode)); in AssembleArchInstruction()
1151 VectorFormat src_f = VectorFormatHalfWidthDoubleLanes(dst_f); in AssembleArchInstruction()
1162 VectorFormat dst_f = VectorFormatFillQ(MiscField::decode(opcode)); in AssembleArchInstruction()
1163 VectorFormat src_f = VectorFormatHalfWidth(dst_f); in AssembleArchInstruction()
1171 VectorFormat dst_f = VectorFormatFillQ(MiscField::decode(opcode)); in AssembleArchInstruction()
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/external/vixl/test/aarch64/
Dtest-simulator-aarch64.cc1449 VectorFormat vd_form, in Test1OpNEON_Helper()
1450 VectorFormat vn_form, in Test1OpNEON_Helper()
1543 VectorFormat vd_form, in Test1OpNEON()
1544 VectorFormat vn_form) { in Test1OpNEON()
1657 VectorFormat vd_form, in Test1OpAcrossNEON_Helper()
1658 VectorFormat vn_form, in Test1OpAcrossNEON_Helper()
1751 VectorFormat vd_form, in Test1OpAcrossNEON()
1752 VectorFormat vn_form) { in Test1OpAcrossNEON()
1885 VectorFormat vd_form, in Test2OpNEON_Helper()
1886 VectorFormat vn_form, in Test2OpNEON_Helper()
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/external/v8/src/wasm/baseline/arm64/
Dliftoff-assembler-arm64.h113 Register rhs, VectorFormat format) { in EmitSimdShift()
136 template <VectorFormat format, ShiftSign sign>
168 LiftoffRegister src, VectorFormat format) { in EmitAllTrue()