Searched refs:WordAccess (Results 1 – 11 of 11) sorted by relevance
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
D | HexagonBaseInfo.h | 52 WordAccess, enumerator 279 case WordAccess: return 4; in getMemAccessSizeInBytes()
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonIsetDx.td | 164 let isCodeGenOnly = 1, mayLoad = 1, accessSize = WordAccess, hasNewValue = 1, opNewValue = 0 in 249 let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in 263 let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in 522 let Uses = [R29], isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in 622 let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in 666 let Uses = [R29], isCodeGenOnly = 1, mayLoad = 1, accessSize = WordAccess, hasNewValue = 1, opNewVa…
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D | HexagonInstrInfoV4.td | 428 let accessSize = WordAccess, hasNewValue = 1 in 431 let accessSize = WordAccess in { 488 let accessSize = WordAccess in { 625 let hasNewValue = 1, accessSize = WordAccess in 716 def S4_storeri_ap : T_ST_absset <"memw", "STriw", IntRegs, 0b100, WordAccess>; 752 def S4_storerinew_ap : T_ST_absset_nv <"memw", "STriw", 0b10, WordAccess>; 793 def S4_storeri_ur : T_StoreAbsReg <"memw", "STriw", IntRegs, 0b100, WordAccess>; 849 def S4_storerinew_ur : T_StoreAbsRegNV <"memw", "STriw", 0b10, WordAccess>; 1027 let accessSize = WordAccess in 1160 let accessSize = WordAccess in [all …]
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D | HexagonInstrInfo.td | 1737 let accessSize = WordAccess, opExtentAlign = 2 in 1748 let accessSize = WordAccess, opExtentAlign = 2 in { 1933 let accessSize = WordAccess, opExtentAlign = 2 in 1946 let accessSize = WordAccess, opExtentAlign = 2, hasNewValue = 0 in { 2017 def L2_loadri_pr : T_load_pr <"memw", IntRegs, 0b1100, WordAccess>; 2023 def L2_loadbzw4_pr : T_load_pr <"memubh", DoubleRegs, 0b0101, WordAccess>; 2085 let accessSize = WordAccess in { 2171 let accessSize = WordAccess in 2174 let accessSize = WordAccess, hasNewValue = 0 in { 2206 let hasNewValue = 1, accessSize = WordAccess, opNewValue = 0 in [all …]
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D | HexagonInstrFormats.td | 60 def WordAccess : MemAccessSize<3>;// Word access instruction (memw).
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
D | HexagonBaseInfo.h | 98 WordAccess = 3, // Word access instruction (memw). enumerator
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D | HexagonMCCodeEmitter.cpp | 393 case HexagonII::MemAccessSize::WordAccess: in getFixupNoBits()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
D | HexagonPseudo.td | 540 defm PS_loadri : NewCircularLoad<IntRegs, WordAccess>; 560 defm PS_storeri : NewCircularStore<IntRegs, WordAccess>; 561 defm PS_storerd : NewCircularStore<DoubleRegs, WordAccess>;
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D | HexagonDepInstrInfo.td | 8988 let accessSize = WordAccess; 9003 let accessSize = WordAccess; 9015 let accessSize = WordAccess; 9028 let accessSize = WordAccess; 9041 let accessSize = WordAccess; 9053 let accessSize = WordAccess; 9172 let accessSize = WordAccess; 9187 let accessSize = WordAccess; 9199 let accessSize = WordAccess; 9212 let accessSize = WordAccess; [all …]
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D | HexagonInstrFormats.td | 32 def WordAccess : MemAccessSize<3>;
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D | HexagonOptAddrMode.cpp | 330 case HexagonII::MemAccessSize::WordAccess: in isValidOffset()
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