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Searched refs:_postdiv2 (Results 1 – 8 of 8) sorted by relevance

/external/u-boot/drivers/clk/rockchip/
Dclk_rk3036.c31 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
33 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
34 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
35 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
36 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
Dclk_rk322x.c28 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
30 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
31 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
32 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
33 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
Dclk_rv1108.c31 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
33 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
34 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
35 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
36 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
Dclk_rk3128.c29 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
31 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
32 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
Dclk_rk3328.c32 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
34 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
35 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
Dclk_rk3399.c44 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
46 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
47 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
Dclk_px30.c31 _postdiv2, _dsmpd, _frac) \ argument
37 .postdiv2 = _postdiv2, \
/external/u-boot/arch/arm/include/asm/arch-rockchip/
Dclock.h51 _postdiv2, _dsmpd, _frac) \ argument
57 .postdiv2 = _postdiv2, \