| /external/tensorflow/tensorflow/python/ops/distributions/ |
| D | exponential.py | 108 self._rate = ops.convert_to_tensor(rate, name="rate")
110 concentration=array_ops.ones([], dtype=self._rate.dtype),
111 rate=self._rate,
116 self._graph_parents += [self._rate]
124 return self._rate
127 return self._log_prob(value) - math_ops.log(self._rate)
130 shape = array_ops.concat([[n], array_ops.shape(self._rate)], 0)
144 return -math_ops.log(sampled) / self._rate
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| D | gamma.py | 173 self._rate = array_ops.identity(rate, name="rate")
175 [self._concentration, self._rate])
183 self._rate],
200 return self._rate
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| /external/u-boot/drivers/clk/uniphier/ |
| D | clk-uniphier.h | 50 #define UNIPHIER_CLK_RATE(_id, _rate) \ argument
55 .fixed_rate = (_rate), \
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| /external/libnl/python/netlink/ |
| D | util.py | 152 self._rate = rate
156 return capi.nl_rate2str(self._rate, self._mode, 32)[1]
159 return self._rate
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| /external/u-boot/drivers/clk/imx/ |
| D | clk-imx8mn.c | 17 #define PLL_1416X_RATE(_rate, _m, _p, _s) \ argument
19 .rate = (_rate), \
25 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \ argument
27 .rate = (_rate), \
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| D | clk-imx8mm.c | 17 #define PLL_1416X_RATE(_rate, _m, _p, _s) \ argument
19 .rate = (_rate), \
25 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \ argument
27 .rate = (_rate), \
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| /external/u-boot/arch/arm/include/asm/arch-rockchip/ |
| D | clock.h | 50 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ argument
53 .rate = _rate##U, \
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| /external/autotest/client/cros/audio/ |
| D | check_quality.py | 280 self._rate = rate
311 normalized_signal, self._rate)
326 rate=self._rate,
347 if not self._raw_data or not self._rate:
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| /external/u-boot/drivers/clk/renesas/ |
| D | renesas-cpg-mssr.h | 79 #define DEF_RATE(_name, _id, _rate) \ argument
80 DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
|
| /external/u-boot/drivers/clk/mediatek/ |
| D | clk-mtk.h | 57 #define FIXED_CLK(_id, _parent, _rate) { \ argument
60 .rate = _rate, \
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| /external/u-boot/arch/arm/include/asm/arch-imx8m/ |
| D | clock.h | 189 #define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \ argument
191 .clk = (_rate), \
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| D | clock_imx8mm.h | 11 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \ argument
13 .rate = (_rate), \
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| /external/tensorflow/tensorflow/core/api_def/base_api/ |
| D | api_def_ApplyAdam.pbtxt | 85 $$lr_t := \text{learning\_rate} * \sqrt{1 - beta_2^t} / (1 - beta_1^t)$$
|
| /external/u-boot/drivers/clk/rockchip/ |
| D | clk_px30.c | 30 #define PX30_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ argument
33 .rate = _rate##U, \
42 #define PX30_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \ argument
44 .rate = _rate##U, \
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| D | clk_rk3308.c | 30 #define RK3308_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \ argument
32 .rate = _rate##U, \
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| /external/iptables/extensions/ |
| D | libxt_rateest.man | 34 be used instead of a negative value. In other words, "max(0, rateest#_rate -
|