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Searched refs:arg10 (Results 1 – 25 of 30) sorted by relevance

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/external/v8/src/third_party/valgrind/
Dvalgrind.h1017 arg7,arg8,arg9,arg10) \ argument
1032 _argvec[10] = (unsigned long)(arg10); \
1056 arg6,arg7,arg8,arg9,arg10, \ argument
1072 _argvec[10] = (unsigned long)(arg10); \
1098 arg6,arg7,arg8,arg9,arg10, \ argument
1114 _argvec[10] = (unsigned long)(arg10); \
1545 arg7,arg8,arg9,arg10) \ argument
1560 _argvec[10] = (unsigned long)(arg10); \
1587 arg7,arg8,arg9,arg10,arg11) \ argument
1602 _argvec[10] = (unsigned long)(arg10); \
[all …]
/external/libchrome/base/third_party/valgrind/
Dvalgrind.h1061 arg7,arg8,arg9,arg10) \ argument
1076 _argvec[10] = (unsigned long)(arg10); \
1100 arg6,arg7,arg8,arg9,arg10, \ argument
1116 _argvec[10] = (unsigned long)(arg10); \
1142 arg6,arg7,arg8,arg9,arg10, \ argument
1158 _argvec[10] = (unsigned long)(arg10); \
1589 arg7,arg8,arg9,arg10) \ argument
1604 _argvec[10] = (unsigned long)(arg10); \
1631 arg7,arg8,arg9,arg10,arg11) \ argument
1646 _argvec[10] = (unsigned long)(arg10); \
[all …]
/external/swiftshader/third_party/subzero/crosstest/
Dtest_calling_conv.cpp49 v4f32 arg10 = {22, 23, 24, 25}; in caller_vlvilvfvdviv() local
54 arg6, arg7, arg8, arg9, arg10, in caller_vlvilvfvdviv()
81 v4f32 arg10, int arg11, v4f32 arg12) { in callee_vlvilvfvdviv() argument
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dret.ll46 …3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, flo…
71 …3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, flo…
85 …3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, flo…
104 …3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, flo…
133 …3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, flo…
162 …3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, flo…
Dcallee-special-input-vgprs.ll243 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
260 store volatile i32 %arg10, i32 addrspace(1)* undef
342 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
347 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
369 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
386 store volatile i32 %arg10, i32 addrspace(1)* undef
493 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
514 store volatile i32 %arg10, i32 addrspace(1)* undef
590 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
611 store volatile i32 %arg10, i32 addrspace(1)* undef
Dllvm.AMDGPU.kill.ll23 …i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,…
Dsmrd.ll109 …i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, flo…
123 …i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, flo…
140 …i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, flo…
155 …i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, flo…
170 …i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, flo…
Dret_jump.ll25 …i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,…
76 …i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,…
Dsgpr-copy.ll7 …i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, flo…
31 …i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, flo…
171 …i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, flo…
224 …i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,…
288 …i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,…
324 …i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,…
Dschedule-kernel-arg-loads.ll26 i64 %arg8, i64 %arg9, i64 %arg10, i64 %arg11, i64 %arg12, i64 %arg13, i64 %arg14, i64 %arg15,
Dsi-scheduler.ll19 …i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,…
Dwait.ll49 …)* byval %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) #0 {
Dunigine-liveness-crash.ll12 …nreg %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <3 x i32> %arg10, <2 x i32> %arg11,…
/external/tensorflow/tensorflow/compiler/mlir/lite/tests/
Dload-quantization-recipe.mlir4 …xf32>, %arg7: tensor<*xf32>, %arg8: tensor<*xf32>, %arg9: tensor<*xf32>, %arg10: tensor<*xf32>, %a…
8 %arg9, %arg10, %arg11, // cell weights
41 // CHECK-NEXT: %[[fo3:.*]] = "tfl.mul"(%arg19, %arg10)
Dops.mlir563 … %arg7: tensor<? x f32>, %arg8: tensor<? x f32>, %arg9: tensor<? x f32>, %arg10: tensor<? x f32>, …
564 …m"(%arg0, %arg1, %arg2, %arg3, %arg4, %arg5, %arg6, %arg7, %arg8, %arg9, %arg10, %arg11, %arg12, %…
565 …m"(%arg0, %arg1, %arg2, %arg3, %arg4, %arg5, %arg6, %arg7, %arg8, %arg9, %arg10, %arg11, %arg12, %…
572 … %arg7: tensor<? x f32>, %arg8: tensor<? x f32>, %arg9: tensor<? x f32>, %arg10: tensor<? x f32>, …
573 …m"(%arg0, %arg1, %arg2, %arg3, %arg4, %arg5, %arg6, %arg7, %arg8, %arg9, %arg10, %arg11, %arg12, %…
574 …m"(%arg0, %arg1, %arg2, %arg3, %arg4, %arg5, %arg6, %arg7, %arg8, %arg9, %arg10, %arg11, %arg12, %…
581 … %arg7: tensor<? x f32>, %arg8: tensor<? x f32>, %arg9: tensor<? x f32>, %arg10: tensor<? x f32>, …
582 …m"(%arg0, %arg1, %arg2, %arg3, %arg4, %arg5, %arg6, %arg7, %arg8, %arg9, %arg10, %arg11, %arg12, %…
583 …m"(%arg0, %arg1, %arg2, %arg3, %arg4, %arg5, %arg6, %arg7, %arg8, %arg9, %arg10, %arg11, %arg12, %…
590 … %arg7: tensor<? x f32>, %arg8: tensor<? x f32>, %arg9: tensor<? x f32>, %arg10: tensor<? x f32>, …
[all …]
/external/mesa3d/include/CL/
Dcl.hpp7664 T10 arg10, in operator ()()
7699 arg10, in operator ()()
7889 T10 arg10, in operator ()()
7923 arg10, in operator ()()
8110 T10 arg10, in operator ()()
8143 arg10, in operator ()()
8327 T10 arg10, in operator ()()
8359 arg10, in operator ()()
8540 T10 arg10, in operator ()()
8571 arg10, in operator ()()
[all …]
/external/tensorflow/tensorflow/compiler/mlir/lite/tests/mlir2flatbuffer/
Dlstm.mlir84 // CHECK-NEXT: name: "arg10",
257 … %arg7: tensor<4 x f32>, %arg8: tensor<4 x f32>, %arg9: tensor<4 x f32>, %arg10: tensor<4 x f32>, …
260 …%24 = "tfl.lstm"(%arg0, %arg1, %arg2, %arg3, %arg4, %arg5, %arg6, %arg7, %arg8, %arg9, %arg10, %ar…
Dunidirectional_sequence_lstm.mlir84 // CHECK-NEXT: name: "arg10",
256 … %arg7: tensor<4 x f32>, %arg8: tensor<4 x f32>, %arg9: tensor<4 x f32>, %arg10: tensor<4 x f32>, …
259 …m"(%arg0, %arg1, %arg2, %arg3, %arg4, %arg5, %arg6, %arg7, %arg8, %arg9, %arg10, %arg11, %arg12, %…
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CFLAliasAnalysis/Steensgaard/
Dstratified-attrs-indexing.ll13 i32* %arg6, i32* %arg7, i32* %arg8, i32* %arg9, i32* %arg10,
/external/llvm/test/Analysis/CFLAliasAnalysis/Steensgaard/
Dstratified-attrs-indexing.ll13 i32* %arg6, i32* %arg7, i32* %arg8, i32* %arg9, i32* %arg10,
/external/llvm/test/CodeGen/AMDGPU/
Dsgpr-copy.ll14 …i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, flo…
38 …i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, flo…
159 …i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, flo…
230 …i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,…
294 …i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,…
324 …i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,…
Dsi-lod-bias.ll9 …i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, flo…
Dschedule-kernel-arg-loads.ll31 i64 %arg8, i64 %arg9, i64 %arg10, i64 %arg11, i64 %arg12, i64 %arg13, i64 %arg14, i64 %arg15,
Dsi-scheduler.ll19 …i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,…
/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
D8bit.pnacl.ll522 …2 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) {
536 %trunc10 = trunc i32 %arg10 to i8

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