| /external/swiftshader/third_party/subzero/crosstest/ |
| D | test_calling_conv.cpp | 50 int arg11 = 26; in caller_vlvilvfvdviv() local
55 arg11, arg12); in caller_vlvilvfvdviv()
81 v4f32 arg10, int arg11, v4f32 arg12) { in callee_vlvilvfvdviv() argument
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | si-scheduler.ll | 19 …32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12,…
25 %i.i = extractelement <2 x i32> %arg11, i32 0
26 %j.i = extractelement <2 x i32> %arg11, i32 1
31 %i.i1 = extractelement <2 x i32> %arg11, i32 0
32 %j.i2 = extractelement <2 x i32> %arg11, i32 1
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| D | ret.ll | 46 …, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, flo…
71 …, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, flo…
85 …, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, flo…
104 …, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, flo…
133 …, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, flo…
162 …, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, flo…
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| D | callee-special-input-vgprs.ll | 243 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
261 store volatile i32 %arg11, i32 addrspace(1)* undef
342 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
347 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
369 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
387 store volatile i32 %arg11, i32 addrspace(1)* undef
493 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
515 store volatile i32 %arg11, i32 addrspace(1)* undef
590 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
612 store volatile i32 %arg11, i32 addrspace(1)* undef
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| D | llvm.AMDGPU.kill.ll | 23 …32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12,…
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| D | smrd.ll | 109 … x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, flo…
123 … x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, flo…
140 … x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, flo…
155 … x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, flo…
170 … x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, flo…
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| D | ret_jump.ll | 25 …32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12,…
76 …32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12,…
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| D | sgpr-copy.ll | 7 … x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, flo…
31 … x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, flo…
171 … x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, flo…
224 …32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, flo…
288 …32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, flo…
324 …32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12,…
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| D | schedule-kernel-arg-loads.ll | 26 i64 %arg8, i64 %arg9, i64 %arg10, i64 %arg11, i64 %arg12, i64 %arg13, i64 %arg14, i64 %arg15,
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| D | unigine-liveness-crash.ll | 12 …32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <3 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12,…
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| D | si-sgpr-spill.ll | 27 …32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, flo…
646 …32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, flo…
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| /external/v8/src/third_party/valgrind/ |
| D | valgrind.h | 1057 arg11) \ argument
1073 _argvec[11] = (unsigned long)(arg11); \
1099 arg11,arg12) \ argument
1115 _argvec[11] = (unsigned long)(arg11); \
1587 arg7,arg8,arg9,arg10,arg11) \ argument
1603 _argvec[11] = (unsigned long)(arg11); \
1631 arg7,arg8,arg9,arg10,arg11,arg12) \ argument
1647 _argvec[11] = (unsigned long)(arg11); \
2040 arg7,arg8,arg9,arg10,arg11) \ argument
2056 _argvec[11] = (unsigned long)arg11; \
[all …]
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| /external/libchrome/base/third_party/valgrind/ |
| D | valgrind.h | 1101 arg11) \ argument
1117 _argvec[11] = (unsigned long)(arg11); \
1143 arg11,arg12) \ argument
1159 _argvec[11] = (unsigned long)(arg11); \
1631 arg7,arg8,arg9,arg10,arg11) \ argument
1647 _argvec[11] = (unsigned long)(arg11); \
1675 arg7,arg8,arg9,arg10,arg11,arg12) \ argument
1691 _argvec[11] = (unsigned long)(arg11); \
2084 arg7,arg8,arg9,arg10,arg11) \ argument
2100 _argvec[11] = (unsigned long)arg11; \
[all …]
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | si-scheduler.ll | 19 …32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12,…
25 %tmp25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %arg5, <2 x i32> %arg11)
26 %tmp26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %arg5, <2 x i32> %arg11)
|
| D | sgpr-copy.ll | 14 … x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, flo…
38 … x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, flo…
159 … x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, flo…
230 …32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, flo…
294 …32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, flo…
324 …32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12,…
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| D | si-lod-bias.ll | 9 … x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, flo…
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| D | schedule-kernel-arg-loads.ll | 31 i64 %arg8, i64 %arg9, i64 %arg10, i64 %arg11, i64 %arg12, i64 %arg13, i64 %arg14, i64 %arg15,
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| D | si-sgpr-spill.ll | 25 …32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, flo…
675 …32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, flo…
|
| /external/tensorflow/tensorflow/compiler/mlir/lite/tests/ |
| D | load-quantization-recipe.mlir | 4 …f32>, %arg8: tensor<*xf32>, %arg9: tensor<*xf32>, %arg10: tensor<*xf32>, %arg11: tensor<*xf32>, %a…
8 %arg9, %arg10, %arg11, // cell weights
82 // CHECK-NEXT: %[[ou3:.*]] = "tfl.mul"(%[[ac3]], %arg11)
|
| D | ops.mlir | 563 …%arg8: tensor<? x f32>, %arg9: tensor<? x f32>, %arg10: tensor<? x f32>, %arg11: tensor<? x f32>, …
564 …, %arg1, %arg2, %arg3, %arg4, %arg5, %arg6, %arg7, %arg8, %arg9, %arg10, %arg11, %arg12, %arg13, %…
565 …, %arg1, %arg2, %arg3, %arg4, %arg5, %arg6, %arg7, %arg8, %arg9, %arg10, %arg11, %arg12, %arg13, %…
572 …%arg8: tensor<? x f32>, %arg9: tensor<? x f32>, %arg10: tensor<? x f32>, %arg11: tensor<? x f32>, …
573 …, %arg1, %arg2, %arg3, %arg4, %arg5, %arg6, %arg7, %arg8, %arg9, %arg10, %arg11, %arg12, %arg13, %…
574 …, %arg1, %arg2, %arg3, %arg4, %arg5, %arg6, %arg7, %arg8, %arg9, %arg10, %arg11, %arg12, %arg13, %…
581 …%arg8: tensor<? x f32>, %arg9: tensor<? x f32>, %arg10: tensor<? x f32>, %arg11: tensor<? x f32>, …
582 …, %arg1, %arg2, %arg3, %arg4, %arg5, %arg6, %arg7, %arg8, %arg9, %arg10, %arg11, %arg12, %arg13, %…
583 …, %arg1, %arg2, %arg3, %arg4, %arg5, %arg6, %arg7, %arg8, %arg9, %arg10, %arg11, %arg12, %arg13, %…
590 …%arg8: tensor<? x f32>, %arg9: tensor<? x f32>, %arg10: tensor<? x f32>, %arg11: tensor<? x f32>, …
[all …]
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| /external/tensorflow/tensorflow/compiler/mlir/lite/tests/mlir2flatbuffer/ |
| D | lstm.mlir | 91 // CHECK-NEXT: name: "arg11",
257 …%arg8: tensor<4 x f32>, %arg9: tensor<4 x f32>, %arg10: tensor<4 x f32>, %arg11: tensor<4 x f32>, …
260 …, %arg1, %arg2, %arg3, %arg4, %arg5, %arg6, %arg7, %arg8, %arg9, %arg10, %arg11, %arg12, %arg13, %…
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| D | unidirectional_sequence_lstm.mlir | 91 // CHECK-NEXT: name: "arg11",
256 …%arg8: tensor<4 x f32>, %arg9: tensor<4 x f32>, %arg10: tensor<4 x f32>, %arg11: tensor<4 x f32>, …
259 …, %arg1, %arg2, %arg3, %arg4, %arg5, %arg6, %arg7, %arg8, %arg9, %arg10, %arg11, %arg12, %arg13, %…
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| /external/mesa3d/include/CL/ |
| D | cl.hpp | 7665 T11 arg11, in operator ()()
7700 arg11, in operator ()()
7890 T11 arg11, in operator ()()
7924 arg11, in operator ()()
8111 T11 arg11, in operator ()()
8144 arg11, in operator ()()
8328 T11 arg11, in operator ()()
8360 arg11, in operator ()()
8541 T11 arg11, in operator ()()
8572 arg11, in operator ()()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CFLAliasAnalysis/Steensgaard/ |
| D | stratified-attrs-indexing.ll | 14 i32* %arg11, i32* %arg12, i32* %arg13, i32* %arg14, i32* %arg15,
|
| /external/llvm/test/Analysis/CFLAliasAnalysis/Steensgaard/ |
| D | stratified-attrs-indexing.ll | 14 i32* %arg11, i32* %arg12, i32* %arg13, i32* %arg14, i32* %arg15,
|