Home
last modified time | relevance | path

Searched refs:base_reg (Results 1 – 21 of 21) sorted by relevance

/external/arm-trusted-firmware/plat/marvell/a3700/common/
Ddram_win.c187 uint32_t base_reg, ctrl_reg, size_reg, enabled, target; in dram_win_map_build() local
200 base_reg = mmio_read_32(CPU_DEC_WIN_BASE_REG(win_id)); in dram_win_map_build()
203 win->base_addr = (base_reg & CPU_DEC_BR_BASE_MASK) >> in dram_win_map_build()
223 uint32_t base_reg, ctrl_reg, size_reg, remap_reg; in cpu_win_set() local
235 base_reg = (uint32_t)(win_cfg->base_addr / in cpu_win_set()
237 base_reg <<= CPU_DEC_BR_BASE_OFFS; in cpu_win_set()
238 base_reg &= CPU_DEC_BR_BASE_MASK; in cpu_win_set()
239 mmio_write_32(CPU_DEC_WIN_BASE_REG(win_id), base_reg); in cpu_win_set()
/external/u-boot/arch/arm/mach-tegra/
Dclock.c592 u32 base_reg, misc_reg; in clock_set_rate() local
598 base_reg = readl(&pll->pll_base); in clock_set_rate()
601 base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift); in clock_set_rate()
602 base_reg |= m << pllinfo->m_shift; in clock_set_rate()
604 base_reg &= ~(pllinfo->n_mask << pllinfo->n_shift); in clock_set_rate()
605 base_reg |= n << pllinfo->n_shift; in clock_set_rate()
607 base_reg &= ~(pllinfo->p_mask << pllinfo->p_shift); in clock_set_rate()
608 base_reg |= p << pllinfo->p_shift; in clock_set_rate()
615 if (base_reg & PLL_BASE_OVRRIDE_MASK) { in clock_set_rate()
616 base_reg |= PLL_ENABLE_MASK; in clock_set_rate()
[all …]
/external/u-boot/drivers/pinctrl/broadcom/
Dpinctrl-bcm283x.c26 u32 *base_reg; member
41 clrsetbits_le32(&priv->base_reg[reg_offset], in bcm2835_gpio_set_func_id()
51 val = readl(&priv->base_reg[BCM2835_GPIO_FSEL_BANK(gpio)]); in bcm2835_gpio_get_func_id()
118 priv->base_reg = dev_read_addr_ptr(dev); in bcm283x_pinctl_probe()
119 if (priv->base_reg == (void *)FDT_ADDR_T_NONE) { in bcm283x_pinctl_probe()
/external/u-boot/drivers/pinctrl/mvebu/
Dpinctrl-mvebu.c48 clrbits_le32(priv->base_reg + AP_EMMC_PHY_CTRL_REG, in mvebu_pinctl_emmc_set_mux()
55 clrbits_le32(priv->base_reg + CP_EMMC_PHY_CTRL_REG, in mvebu_pinctl_emmc_set_mux()
113 clrsetbits_le32(priv->base_reg + reg_offset, in mvebu_pinctrl_set_state()
174 clrsetbits_le32(priv->base_reg + reg_offset, in mvebu_pinctrl_set_state_all()
194 priv->base_reg = devfdt_get_addr_ptr(dev); in mvebu_pinctl_probe()
195 if (priv->base_reg == (void *)FDT_ADDR_T_NONE) { in mvebu_pinctl_probe()
Dpinctrl-mvebu.h23 void *base_reg; member
/external/mesa3d/src/util/
Dregister_allocate.h60 unsigned int base_reg, unsigned int reg);
64 unsigned int base_reg, unsigned int reg0, unsigned int reg1);
Dregister_allocate.c282 unsigned int base_reg, unsigned int reg) in ra_add_transitive_reg_conflict() argument
284 ra_add_reg_conflict(regs, reg, base_reg); in ra_add_transitive_reg_conflict()
286 util_dynarray_foreach(&regs->regs[base_reg].conflict_list, unsigned int, in ra_add_transitive_reg_conflict()
301 unsigned int base_reg, unsigned int reg0, unsigned int reg1) in ra_add_transitive_reg_pair_conflict() argument
303 ra_add_reg_conflict(regs, reg0, base_reg); in ra_add_transitive_reg_pair_conflict()
304 ra_add_reg_conflict(regs, reg1, base_reg); in ra_add_transitive_reg_pair_conflict()
306 util_dynarray_foreach(&regs->regs[base_reg].conflict_list, unsigned int, i) { in ra_add_transitive_reg_pair_conflict()
/external/mesa3d/src/intel/compiler/
Dbrw_fs_reg_allocate.cpp228 for (int base_reg = j; in brw_alloc_reg_set() local
229 base_reg < j + (class_sizes[i] + 1) / 2; in brw_alloc_reg_set()
230 base_reg++) { in brw_alloc_reg_set()
231 ra_add_reg_conflict(regs, base_reg, reg); in brw_alloc_reg_set()
242 for (int base_reg = j; in brw_alloc_reg_set() local
243 base_reg < j + class_sizes[i]; in brw_alloc_reg_set()
244 base_reg++) { in brw_alloc_reg_set()
245 ra_add_reg_conflict(regs, base_reg, reg); in brw_alloc_reg_set()
Dbrw_vec4_reg_allocate.cpp138 for (int base_reg = j; in brw_vec4_alloc_reg_set() local
139 base_reg < j + class_sizes[i]; in brw_vec4_alloc_reg_set()
140 base_reg++) { in brw_vec4_alloc_reg_set()
141 ra_add_reg_conflict(compiler->vec4_reg_set.regs, base_reg, reg); in brw_vec4_alloc_reg_set()
/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_state_init.c426 uint32_t base_reg; in cube_emit_cs() local
439 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break; in cube_emit_cs()
440 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break; in cube_emit_cs()
442 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break; in cube_emit_cs()
448 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0)); in cube_emit_cs()
/external/mesa3d/src/amd/vulkan/
Dradv_cmd_buffer.c710 uint32_t base_reg = pipeline->user_data_0[stage]; in radv_emit_userdata_address() local
717 base_reg + loc->sgpr_idx * 4, va, false); in radv_emit_userdata_address()
940 uint32_t base_reg = pipeline->user_data_0[stage]; in radv_emit_inline_push_consts() local
946 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count); in radv_emit_inline_push_consts()
2847 uint32_t base_reg; in radv_emit_streamout_buffers() local
2858 base_reg = pipeline->user_data_0[stage]; in radv_emit_streamout_buffers()
2861 base_reg + loc->sgpr_idx * 4, va, false); in radv_emit_streamout_buffers()
2867 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0; in radv_emit_streamout_buffers()
2870 base_reg + loc->sgpr_idx * 4, va, false); in radv_emit_streamout_buffers()
2951 uint32_t base_reg; in radv_flush_ngg_gs_state() local
[all …]
/external/v8/src/builtins/x64/
Dbuiltins-x64.cc3707 Register base_reg = r15; in CallApiFunctionAndReturn() local
3708 __ Move(base_reg, next_address); in CallApiFunctionAndReturn()
3709 __ movq(prev_next_address_reg, Operand(base_reg, kNextOffset)); in CallApiFunctionAndReturn()
3710 __ movq(prev_limit_reg, Operand(base_reg, kLimitOffset)); in CallApiFunctionAndReturn()
3711 __ addl(Operand(base_reg, kLevelOffset), Immediate(1)); in CallApiFunctionAndReturn()
3742 __ subl(Operand(base_reg, kLevelOffset), Immediate(1)); in CallApiFunctionAndReturn()
3743 __ movq(Operand(base_reg, kNextOffset), prev_next_address_reg); in CallApiFunctionAndReturn()
3744 __ cmpq(prev_limit_reg, Operand(base_reg, kLimitOffset)); in CallApiFunctionAndReturn()
3815 __ movq(Operand(base_reg, kLimitOffset), prev_limit_reg); in CallApiFunctionAndReturn()
/external/v8/src/diagnostics/x64/
Ddisasm-x64.cc336 int base_reg(int low_bits) { return low_bits | ((rex_ & 0x01) << 3); } in base_reg() function in disasm::DisassemblerX64
2586 NameOfCPURegister(base_reg(current & 0x07))); in InstructionDecode()
2591 NameOfCPURegister(base_reg(current & 0x07))); in InstructionDecode()
2613 NameOfCPURegister(base_reg(current & 0x07)), in InstructionDecode()
/external/mesa3d/src/freedreno/decode/
Dcffdec.c1441 const unsigned base_reg = in cp_load_state() local
1447 const unsigned reg = base_reg + (dwords[1] >> 28) * 2; in cp_load_state()
1451 const unsigned reg = base_reg + (dwords[1] >> 28); in cp_load_state()
/external/v8/src/interpreter/
Dinterpreter-assembler.cc298 TNode<IntPtrT> base_reg = RegisterLocation( in GetRegisterListAtOperandIndex() local
301 return RegListNodePair(base_reg, reg_count); in GetRegisterListAtOperandIndex()
/external/pcre/dist2/src/
Dpcre2_jit_compile.c2328 int from_sp, base_reg, offset, i; in copy_recurse_data() local
2343 base_reg = STACK_TOP; in copy_recurse_data()
2350 base_reg = STACK_TOP; in copy_recurse_data()
2356 base_reg = TMP2; in copy_recurse_data()
2366 if (base_reg != TMP2) in copy_recurse_data()
2393 delayed_mem_copy_move(&status, base_reg, stackptr, SLJIT_SP, common->recursive_head_ptr); in copy_recurse_data()
2396 delayed_mem_copy_move(&status, SLJIT_SP, common->recursive_head_ptr, base_reg, stackptr); in copy_recurse_data()
2405 delayed_mem_copy_move(&status, base_reg, stackptr, SLJIT_SP, common->control_head_ptr); in copy_recurse_data()
2408 delayed_mem_copy_move(&status, SLJIT_SP, common->control_head_ptr, base_reg, stackptr); in copy_recurse_data()
2679 delayed_mem_copy_move(&status, base_reg, stackptr, SLJIT_SP, private_srcw[i]); in copy_recurse_data()
[all …]
/external/v8/src/compiler/backend/mips/
Dcode-generator-mips.cc919 Register base_reg = offset.from_stack_pointer() ? sp : fp; in AssembleArchInstruction() local
920 __ Addu(i.OutputRegister(), base_reg, Operand(offset.offset())); in AssembleArchInstruction()
934 __ Addu(kScratchReg, base_reg, Operand(offset.offset())); in AssembleArchInstruction()
941 __ Addu(kScratchReg, base_reg, Operand(offset.offset())); in AssembleArchInstruction()
/external/v8/src/compiler/backend/mips64/
Dcode-generator-mips64.cc898 Register base_reg = offset.from_stack_pointer() ? sp : fp; in AssembleArchInstruction() local
899 __ Daddu(i.OutputRegister(), base_reg, Operand(offset.offset())); in AssembleArchInstruction()
912 __ Daddu(kScratchReg, base_reg, Operand(offset.offset())); in AssembleArchInstruction()
919 __ Daddu(kScratchReg, base_reg, Operand(offset.offset())); in AssembleArchInstruction()
/external/pcre/dist2/src/sljit/
DsljitNativeARM_32.c891 #define EMIT_DATA_TRANSFER(type, add, target_reg, base_reg, arg) \ argument
892 (data_transfer_insts[(type) & 0xf] | ((add) << 23) | RD(target_reg) | RN(base_reg) | (arg))
/external/v8/src/codegen/x64/
Dassembler-x64.cc143 int base_reg = (has_sib ? operand.data().buf[1] : modrm) & 0x07; in Operand() local
146 bool is_baseless = (mode == 0) && (base_reg == 0x05); // No base or RIP base. in Operand()
168 } else if (disp_value != 0 || (base_reg == 0x05)) { in Operand()
/external/v8/src/execution/s390/
Dsimulator-s390.cc2926 #define GET_ADDRESS(index_reg, base_reg, offset) \ argument
2928 (((base_reg) == 0) ? 0 : get_register(base_reg)) + offset