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Searched refs:bit0 (Results 1 – 25 of 42) sorted by relevance

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/external/libxaac/decoder/
Dixheaacd_sbr_crc.c35 WORD32 bit0, bit1; in ixheaacd_calc_chk_sum() local
36 bit0 = ((crc_state_local & crc_mask) ? 1 : 0); in ixheaacd_calc_chk_sum()
38 bit0 ^= bit1; in ixheaacd_calc_chk_sum()
40 if (bit0) { in ixheaacd_calc_chk_sum()
/external/mesa3d/src/intel/compiler/
Dtest_eu_compact.cpp147 for (int bit0 = 0; bit0 < 128; bit0++) { in test_fuzz_compact_instruction() local
148 if (skip_bit(p->devinfo, &src, bit0)) in test_fuzz_compact_instruction()
158 bits[bit0 / 64] ^= (1ull << (bit0 & 63)); in test_fuzz_compact_instruction()
167 printf(" twiddled bits for fuzzing %d, %d\n", bit0, bit1); in test_fuzz_compact_instruction()
/external/u-boot/tools/
Dvybridimage.c42 uint8_t bit0 = (byte & (1 << 0)) ? 1 : 0; in vybridimage_sw_ecc() local
54 res |= ((bit7 ^ bit6 ^ bit5 ^ bit1 ^ bit0) << 2); in vybridimage_sw_ecc()
55 res |= ((bit7 ^ bit4 ^ bit3 ^ bit0) << 3); in vybridimage_sw_ecc()
56 res |= ((bit6 ^ bit4 ^ bit3 ^ bit2 ^ bit1 ^ bit0) << 4); in vybridimage_sw_ecc()
/external/u-boot/board/Seagate/nas220/
Dkwbimage.cfg80 # bit0: 0, OpenPage enabled
99 # bit0: 0, DDR DLL enabled
123 # bit0: 1, Window enabled
145 #bit0=1, enable DDR init upon this register write
/external/u-boot/board/Seagate/goflexhome/
Dkwbimage.cfg81 # bit0: 0, OpenPage enabled
99 # bit0: 0, DDR DLL enabled
127 # bit0: 1, Window enabled
147 #bit0=1, enable DDR init upon this register write
/external/u-boot/board/Marvell/guruplug/
Dkwbimage.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 1, Window enabled
141 #bit0=1, enable DDR init upon this register write
/external/u-boot/board/Seagate/dockstar/
Dkwbimage.cfg78 # bit0: 0, OpenPage enabled
96 # bit0: 0, DDR DLL enabled
124 # bit0: 1, Window enabled
144 #bit0=1, enable DDR init upon this register write
/external/u-boot/board/Marvell/dreamplug/
Dkwbimage.cfg76 # bit0: 0, OpenPage enabled
94 # bit0: 0, DDR DLL enabled
122 # bit0: 1, Window enabled
142 #bit0=1, enable DDR init upon this register write
/external/u-boot/board/Marvell/sheevaplug/
Dkwbimage.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 1, Window enabled
141 #bit0=1, enable DDR init upon this register write
/external/u-boot/board/Synology/ds109/
Dkwbimage.cfg79 # bit0: 0, OpenPage enabled
97 # bit0: 0, DDR DLL enabled
125 # bit0: 1, Window enabled
147 #bit0=1, enable DDR init upon this register write
/external/u-boot/board/Marvell/openrd/
Dkwbimage.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 1, Window enabled
147 #bit0=1, enable DDR init upon this register write
/external/u-boot/board/keymile/km_arm/
Dkwbimage.cfg96 # bit0: 0, OpenPage enabled
105 # bit0: 0, DDR DLL enabled
132 # bit0: 1, Window enabled
158 # bit0=1, enable DDR init upon this register write
Dkwbimage-memphis.cfg99 # bit0: 0, OpenPage enabled
108 # bit0: 0, DDR DLL enabled
147 # bit0: 1, Window enabled
176 # bit0=1, enable DDR init upon this register write
/external/u-boot/board/LaCie/netspace_v2/
Dkwbimage-is2.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 1, Window enabled
146 #bit0=1, enable DDR init upon this register write
Dkwbimage.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 1, Window enabled
146 #bit0=1, enable DDR init upon this register write
Dkwbimage-ns2l.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 1, Window enabled
146 #bit0=1, enable DDR init upon this register write
/external/u-boot/board/raidsonic/ib62x0/
Dkwbimage.cfg76 # bit0: 0, OpenPage enabled
94 # bit0: 0, DDR DLL enabled
122 # bit0: 0x1, Window enabled
147 # bit0: 0x1, enable DDR init upon this register write
/external/u-boot/board/LaCie/net2big_v2/
Dkwbimage.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 1, Window enabled
146 #bit0=1, enable DDR init upon this register write
/external/u-boot/board/iomega/iconnect/
Dkwbimage.cfg75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
121 # bit0: 0x1, Window enabled
146 # bit0: 0x1, enable DDR init upon this register write
/external/u-boot/board/cloudengines/pogo_e02/
Dkwbimage.cfg79 # bit0: 0, OpenPage enabled
97 # bit0: 0, DDR DLL enabled
125 # bit0: 1, Window enabled
150 #bit0=1, enable DDR init upon this register write
/external/u-boot/board/d-link/dns325/
Dkwbimage.cfg85 # bit0: 0, OPEn=OpenPage enabled
103 # bit0: 0, DRAM DLL enabled
143 # bit0: 1, Window enabled
151 # bit0: 1, Window enabled
186 # bit0: 1, enable DDR init upon this register write
/external/swiftshader/third_party/astc-encoder/Source/
Dastc_color_unquantize.cpp389 int bit0 = (v1 >> 6) & 1; in hdr_rgbo_unpack3() local
400 green |= bit0 << 6; in hdr_rgbo_unpack3()
428 red |= bit0 << 8; in hdr_rgbo_unpack3()
431 red |= bit0 << 9; in hdr_rgbo_unpack3()
535 int bit0 = (v2 >> 6) & 1; in hdr_rgb_unpack3() local
546 a |= bit0 << 9; in hdr_rgb_unpack3()
569 b0 |= bit0 << 6; in hdr_rgb_unpack3()
/external/libcups/filter/
Drastertohp.c565 bit0, /* Current low bit data */ in OutputLine() local
610bit0 = (unsigned char)(((bit & 64) << 1) | ((bit & 16) << 2) | ((bit & 4) << 3) | ((bit & 1) << 4)… in OutputLine()
617bit0 |= (unsigned char)((bit & 1) | ((bit & 4) >> 1) | ((bit & 16) >> 2) | ((bit & 64) >> 3)); in OutputLine()
621 bit_ptr[0] = bit0; in OutputLine()
/external/u-boot/board/buffalo/lsxl/
Dkwbimage-lsxhl.cfg91 # bit0: 0, OPEn=OpenPage enabled
112 # bit0: 0, DRAM DLL enabled
159 # bit0: 1, Window enabled
207 # bit0: 1, enable DDR init upon this register write
Dkwbimage-lschl.cfg91 # bit0: 0, OPEn=OpenPage enabled
112 # bit0: 0, DRAM DLL enabled
159 # bit0: 1, Window enabled
207 # bit0: 1, enable DDR init upon this register write

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