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/external/arm-trusted-firmware/include/lib/cpus/aarch32/
Dcortex_a53.h27 #define CORTEX_A53_ECTLR p15, 1, c15
40 #define CORTEX_A53_MERRSR p15, 2, c15
45 #define CORTEX_A53_CPUACTLR p15, 0, c15
55 #define CORTEX_A53_L2ACTLR p15, 1, c15, c0, 0
71 #define CORTEX_A53_L2MERRSR p15, 3, c15
Dcortex_a72.h18 #define CORTEX_A72_ECTLR p15, 1, c15
28 #define CORTEX_A72_MERRSR p15, 2, c15
33 #define CORTEX_A72_CPUACTLR p15, 0, c15
56 #define CORTEX_A72_L2MERRSR p15, 3, c15
Dcortex_a57.h27 #define CORTEX_A57_ECTLR p15, 1, c15
40 #define CORTEX_A57_CPUMERRSR p15, 2, c15
45 #define CORTEX_A57_CPUACTLR p15, 0, c15
82 #define CORTEX_A57_L2MERRSR p15, 3, c15
Dcortex_a32.h19 #define CORTEX_A32_CPUECTLR_EL1 p15, 1, c15
Dcortex_a17.h25 #define CORTEX_A17_IMP_DEF_REG1 p15, 0, c15, c0, 1
Dcortex_a15.h15 #define CORTEX_A15_ACTLR2 p15, 1, c15, c0, 4
Dcortex_a9.h26 #define PCR p15, 0, c15, c0, 0
/external/u-boot/arch/arm/cpu/armv7/
Dstart.S172 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
174 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
178 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
180 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
184 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
186 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
189 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
191 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
195 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
197 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
[all …]
/external/arm-trusted-firmware/include/arch/aarch32/
Darch.h691 #define AMEVTYPER18 p15, 0, c13, c15, 0
692 #define AMEVTYPER19 p15, 0, c13, c15, 1
693 #define AMEVTYPER1A p15, 0, c13, c15, 2
694 #define AMEVTYPER1B p15, 0, c13, c15, 3
695 #define AMEVTYPER1C p15, 0, c13, c15, 4
696 #define AMEVTYPER1D p15, 0, c13, c15, 5
697 #define AMEVTYPER1E p15, 0, c13, c15, 6
698 #define AMEVTYPER1F p15, 0, c13, c15, 7
/external/clang/test/CodeGen/
Dstruct.c138 struct a15 {char a; int b[];} c15; variable
139 int a16(void) {c15.a = 1;} in a16()
/external/u-boot/arch/arm/include/asm/arch-mx35/
Dlowlevel_macro.S116 mcr p15, 0, r0, c15, c2, 4
124 mcr p15, 0, r0, c15, c2, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/SystemZ/
Dregs-good.s128 #CHECK: lctl %c14, %c15, 0 # encoding: [0xb7,0xef,0x00,0x00]
137 lctl %c14,%c15,0
203 #CHECK: .cfi_offset %c15, 438
269 .cfi_offset %c15,438
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dreadcyclecounter.ll4 ; CHECK: r1:0 = c15:14
/external/deqp-deps/glslang/Test/
Dhlsl.buffer.frag25 column_major float3x4 m3 : packoffset(c15);
DstringToDouble.vert71 double c15 = 000120030000.0045600000e4;
/external/u-boot/board/freescale/mx31pdk/
Dlowlevel_init.S14 mcr p15, 0, r0, c15, c2, 4
/external/angle/third_party/glslang/src/Test/
Dhlsl.buffer.frag25 column_major float3x4 m3 : packoffset(c15);
DstringToDouble.vert71 double c15 = 000120030000.0045600000e4;
/external/mesa3d/src/freedreno/.gitlab-ci/reference/
Dfd-clouds.log2343 :2:0254:0398[40700027x_103f001ax] mul.f r9.w, r6.z, c15.w
2369 :3:0280:0450[638d8025x_0026103cx] mad.f32 r9.y, c15.x, r6.w, r9.z
2371 :3:0282:0452[63918025x_0025103dx] mad.f32 r9.y, c15.y, r8.w, r9.y
2383 :2:0294:0478[4070081bx_000f103ex] (nop1) mul.f r6.w, c15.z, r3.w
2402 :2:0313:0510[40700029x_103f0025x] mul.f r10.y, r9.y, c15.w
2426 :3:0337:0558[63920027x_0027103cx] mad.f32 r9.w, c15.x, r9.x, r9.w
2430 :3:0341:0562[63918027x_0027103dx] mad.f32 r9.w, c15.y, r8.w, r9.w
2461 :2:0372:0624[4070002ax_103f0025x] mul.f r10.z, r9.y, c15.w
2485 :3:0396:0672[63930028x_0028103cx] mad.f32 r10.x, c15.x, r9.z, r10.x
2488 :3:0399:0675[63918028x_0028103dx] mad.f32 r10.x, c15.y, r8.w, r10.x
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Darm64-system.txt50 # CHECK: sysl x20, #6, c3, c15, #7
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-system.txt50 # CHECK: sysl x20, #6, c3, c15, #7
/external/capstone/suite/MC/ARM/
Dbasic-arm-instructions.s.cs302 0x12,0xf7,0x7b,0xec = ldcl p7, c15, [r11], #-72
314 0x12,0xf7,0x7b,0x8c = ldclhi p7, c15, [r11], #-72
378 0xd6,0xff,0xff,0xee = mrc p15, #7, apsr_nzcv, c15, c6, #6
380 0x30,0xf9,0xff,0xfe = mrc2 p9, #7, apsr_nzcv, c15, c0, #1
381 0xd6,0xff,0xff,0x0e = mrceq p15, #7, apsr_nzcv, c15, c6, #6
787 0x12,0xf7,0x6b,0xec = stcl p7, c15, [r11], #-72
799 0x12,0xf7,0x6b,0x8c = stclhi p7, c15, [r11], #-72
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dra-allocatable.ll78 @c15 = external global i32*
237 %91 = load i32*, i32** @c15, align 4
/external/llvm/test/CodeGen/Mips/
Dra-allocatable.ll78 @c15 = external global i32*
237 %91 = load i32*, i32** @c15, align 4
/external/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td162 def UPCH : Rc<15, "upcyclehi", ["c15"]>, DwarfRegNum<[82]>;
174 def UPC : Rcc<14, "c15:14", [UPCL, UPCH]>, DwarfRegNum<[80]>;

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