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Searched refs:chan (Results 1 – 25 of 337) sorted by relevance

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/external/wpa_supplicant_8/src/ap/
Dacs.c249 static void acs_clean_chan_surveys(struct hostapd_channel_data *chan) in acs_clean_chan_surveys() argument
253 if (dl_list_empty(&chan->survey_list)) in acs_clean_chan_surveys()
256 dl_list_for_each_safe(survey, tmp, &chan->survey_list, in acs_clean_chan_surveys()
267 struct hostapd_channel_data *chan; in acs_cleanup_mode() local
270 chan = &mode->channels[i]; in acs_cleanup_mode()
272 if (chan->flag & HOSTAPD_CHAN_SURVEY_LIST_INITIALIZED) in acs_cleanup_mode()
273 acs_clean_chan_surveys(chan); in acs_cleanup_mode()
275 dl_list_init(&chan->survey_list); in acs_cleanup_mode()
276 chan->flag |= HOSTAPD_CHAN_SURVEY_LIST_INITIALIZED; in acs_cleanup_mode()
277 chan->min_nf = 0; in acs_cleanup_mode()
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Ddfs.c54 static int dfs_channel_available(struct hostapd_channel_data *chan, in dfs_channel_available() argument
62 if (skip_radar && (chan->flag & HOSTAPD_CHAN_RADAR) && in dfs_channel_available()
63 ((chan->flag & HOSTAPD_CHAN_DFS_MASK) != in dfs_channel_available()
67 if (chan->flag & HOSTAPD_CHAN_DISABLED) in dfs_channel_available()
69 if ((chan->flag & HOSTAPD_CHAN_RADAR) && in dfs_channel_available()
70 ((chan->flag & HOSTAPD_CHAN_DFS_MASK) == in dfs_channel_available()
77 static int dfs_is_chan_allowed(struct hostapd_channel_data *chan, int n_chans) in dfs_is_chan_allowed() argument
117 if (chan->chan == allowed[i]) in dfs_is_chan_allowed()
143 struct hostapd_channel_data *first_chan, *chan; in dfs_chan_range_available() local
164 chan = dfs_get_chan_data(mode, first_chan->freq + i * 20, in dfs_chan_range_available()
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/external/u-boot/drivers/ddr/marvell/axp/
Dxor.c20 static int mv_xor_cmd_set(u32 chan, int command);
21 static int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl);
140 static int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl) in mv_xor_ctrl_set() argument
145 val = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))) in mv_xor_ctrl_set()
149 reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), xor_ctrl); in mv_xor_ctrl_set()
154 int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size, u32 init_val_high, in mv_xor_mem_init() argument
160 if (chan >= MV_XOR_MAX_CHAN) in mv_xor_mem_init()
163 if (MV_ACTIVE == mv_xor_state_get(chan)) in mv_xor_mem_init()
171 tmp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_mem_init()
174 reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), tmp); in mv_xor_mem_init()
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Dxor_regs.h13 #define XOR_UNIT(chan) ((chan) >> 1) argument
14 #define XOR_CHAN(chan) ((chan) & 1) argument
25 #define XOR_CONFIG_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x10 + ((chan) * 4))) argument
26 #define XOR_ACTIVATION_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x20 + ((chan) * 4))) argument
35 #define XOR_NEXT_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x200 + ((chan) * 4))) argument
36 #define XOR_CURR_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x210 + ((chan) * 4))) argument
37 #define XOR_BYTE_COUNT_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x220 + ((chan) * 4))) argument
39 #define XOR_DST_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x2B0 + ((chan) * 4))) argument
40 #define XOR_BLOCK_SIZE_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x2C0 + ((chan) * 4))) argument
100 #define XOR_WINDOW_CTRL_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x240 + ((chan) * 4))) argument
/external/u-boot/drivers/ddr/marvell/a38x/
Dxor.c151 int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl) in mv_xor_ctrl_set() argument
156 old_value = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))) & in mv_xor_ctrl_set()
160 reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), xor_ctrl); in mv_xor_ctrl_set()
165 int mv_xor_mem_init(u32 chan, u32 start_ptr, unsigned long long block_size, in mv_xor_mem_init() argument
174 if (chan >= MV_XOR_MAX_CHAN) in mv_xor_mem_init()
177 if (MV_ACTIVE == mv_xor_state_get(chan)) in mv_xor_mem_init()
185 temp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_mem_init()
188 reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), temp); in mv_xor_mem_init()
194 reg_write(XOR_DST_PTR_REG(XOR_UNIT(chan), XOR_CHAN(chan)), start_ptr); in mv_xor_mem_init()
200 reg_write(XOR_BLOCK_SIZE_REG(XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_mem_init()
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Dxor_regs.h13 #define XOR_UNIT(chan) ((chan) >> 1) argument
14 #define XOR_CHAN(chan) ((chan) & 1) argument
21 #define XOR_CONFIG_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ argument
22 (0x10 + ((chan) * 4)))
23 #define XOR_ACTIVATION_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ argument
24 (0x20 + ((chan) * 4)))
33 #define XOR_NEXT_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ argument
34 (0x200 + ((chan) * 4)))
35 #define XOR_CURR_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ argument
36 (0x210 + ((chan) * 4)))
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/external/u-boot/drivers/pwm/
Dsandbox_pwm.c33 struct sandbox_pwm_chan chan[NUM_CHANNELS]; member
40 struct sandbox_pwm_chan *chan; in sandbox_pwm_get_config() local
44 chan = &priv->chan[channel]; in sandbox_pwm_get_config()
45 *period_nsp = chan->period_ns; in sandbox_pwm_get_config()
46 *duty_nsp = chan->duty_ns; in sandbox_pwm_get_config()
47 *enablep = chan->enable; in sandbox_pwm_get_config()
48 *polarityp = chan->polarity; in sandbox_pwm_get_config()
57 struct sandbox_pwm_chan *chan; in sandbox_pwm_set_config() local
61 chan = &priv->chan[channel]; in sandbox_pwm_set_config()
62 chan->period_ns = period_ns; in sandbox_pwm_set_config()
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/external/mesa3d/src/gallium/drivers/r300/compiler/
Dradeon_dataflow_swizzles.c48 for(unsigned int chan = 0; chan < 4; ++chan) { in rewrite_source() local
49 if (GET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan) != RC_SWIZZLE_UNUSED) in rewrite_source()
50 usemask |= 1 << chan; in rewrite_source()
68 for(unsigned int chan = 0; chan < 4; ++chan) { in rewrite_source() local
69 if (!GET_BIT(split.Phase[phase], chan)) in rewrite_source()
70 SET_SWZ(mov->U.I.SrcReg[0].Swizzle, chan, RC_SWIZZLE_UNUSED); in rewrite_source()
72 phase_refmask |= 1 << GET_SWZ(mov->U.I.SrcReg[0].Swizzle, chan); in rewrite_source()
90 for(unsigned int chan = 0; chan < 4; ++chan) { in rewrite_source() local
91 SET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan, in rewrite_source()
92 GET_BIT(usemask, chan) ? chan : RC_SWIZZLE_UNUSED); in rewrite_source()
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/external/u-boot/drivers/mailbox/
Dmailbox-uclass.c17 static int mbox_of_xlate_default(struct mbox_chan *chan, in mbox_of_xlate_default() argument
20 debug("%s(chan=%p)\n", __func__, chan); in mbox_of_xlate_default()
27 chan->id = args->args[0]; in mbox_of_xlate_default()
32 int mbox_get_by_index(struct udevice *dev, int index, struct mbox_chan *chan) in mbox_get_by_index() argument
39 debug("%s(dev=%p, index=%d, chan=%p)\n", __func__, dev, index, chan); in mbox_get_by_index()
66 chan->dev = dev_mbox; in mbox_get_by_index()
68 ret = ops->of_xlate(chan, &args); in mbox_get_by_index()
70 ret = mbox_of_xlate_default(chan, &args); in mbox_get_by_index()
77 ret = ops->request(chan); in mbox_get_by_index()
87 struct mbox_chan *chan) in mbox_get_by_name() argument
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Dstm32-ipcc.c26 #define RX_BIT_CHAN(chan) BIT(chan) argument
28 #define TX_BIT_CHAN(chan) BIT(TX_BIT_SHIFT + (chan)) argument
39 static int stm32_ipcc_request(struct mbox_chan *chan) in stm32_ipcc_request() argument
41 struct stm32_ipcc *ipcc = dev_get_priv(chan->dev); in stm32_ipcc_request()
43 debug("%s(chan=%p)\n", __func__, chan); in stm32_ipcc_request()
45 if (chan->id >= ipcc->n_chans) { in stm32_ipcc_request()
47 __func__, chan->id); in stm32_ipcc_request()
54 static int stm32_ipcc_free(struct mbox_chan *chan) in stm32_ipcc_free() argument
56 debug("%s(chan=%p)\n", __func__, chan); in stm32_ipcc_free()
61 static int stm32_ipcc_send(struct mbox_chan *chan, const void *data) in stm32_ipcc_send() argument
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Dsandbox-mbox.c23 static int sandbox_mbox_request(struct mbox_chan *chan) in sandbox_mbox_request() argument
25 debug("%s(chan=%p)\n", __func__, chan); in sandbox_mbox_request()
27 if (chan->id >= SANDBOX_MBOX_CHANNELS) in sandbox_mbox_request()
33 static int sandbox_mbox_free(struct mbox_chan *chan) in sandbox_mbox_free() argument
35 debug("%s(chan=%p)\n", __func__, chan); in sandbox_mbox_free()
40 static int sandbox_mbox_send(struct mbox_chan *chan, const void *data) in sandbox_mbox_send() argument
42 struct sandbox_mbox *sbm = dev_get_priv(chan->dev); in sandbox_mbox_send()
45 debug("%s(chan=%p, data=%p)\n", __func__, chan, data); in sandbox_mbox_send()
47 sbm->chans[chan->id].rx_msg = *pmsg ^ SANDBOX_MBOX_PING_XOR; in sandbox_mbox_send()
48 sbm->chans[chan->id].rx_msg_valid = true; in sandbox_mbox_send()
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Dtegra-hsp.c71 static int tegra_hsp_of_xlate(struct mbox_chan *chan, in tegra_hsp_of_xlate() argument
74 debug("%s(chan=%p)\n", __func__, chan); in tegra_hsp_of_xlate()
81 chan->id = (args->args[0] << 16) | args->args[1]; in tegra_hsp_of_xlate()
86 static int tegra_hsp_request(struct mbox_chan *chan) in tegra_hsp_request() argument
90 debug("%s(chan=%p)\n", __func__, chan); in tegra_hsp_request()
92 db_id = tegra_hsp_db_id(chan->id); in tegra_hsp_request()
101 static int tegra_hsp_free(struct mbox_chan *chan) in tegra_hsp_free() argument
103 debug("%s(chan=%p)\n", __func__, chan); in tegra_hsp_free()
108 static int tegra_hsp_send(struct mbox_chan *chan, const void *data) in tegra_hsp_send() argument
110 struct tegra_hsp *thsp = dev_get_priv(chan->dev); in tegra_hsp_send()
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/external/mesa3d/src/amd/llvm/
Dac_llvm_cull.c144 for (unsigned chan = 0; chan < (cull_view_near_z || cull_view_far_z ? 3 : 2); chan++) { in cull_bbox() local
145 bbox_min[chan] = ac_build_fmin(ctx, pos[0][chan], pos[1][chan]); in cull_bbox()
146 bbox_min[chan] = ac_build_fmin(ctx, bbox_min[chan], pos[2][chan]); in cull_bbox()
148 bbox_max[chan] = ac_build_fmax(ctx, pos[0][chan], pos[1][chan]); in cull_bbox()
149 bbox_max[chan] = ac_build_fmax(ctx, bbox_max[chan], pos[2][chan]); in cull_bbox()
154 for (unsigned chan = 0; chan < 3; chan++) { in cull_bbox() local
157 if ((cull_view_xy && chan <= 1) || (cull_view_near_z && chan == 2)) { in cull_bbox()
158 float t = chan == 2 && use_halfz_clip_space ? 0 : -1; in cull_bbox()
159 visible = LLVMBuildFCmp(builder, LLVMRealOGE, bbox_max[chan], in cull_bbox()
164 if ((cull_view_xy && chan <= 1) || (cull_view_far_z && chan == 2)) { in cull_bbox()
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/external/mesa3d/src/gallium/auxiliary/gallivm/
Dlp_bld_tgsi_info.c64 unsigned chan) in analyse_src() argument
68 unsigned swizzle = tgsi_util_get_src_register_swizzle(src, chan); in analyse_src()
111 unsigned chan; in analyse_tex() local
172 for (chan = 0; chan < 4; ++chan) { in analyse_tex()
173 struct lp_tgsi_channel_info *chan_info = &tex_info->coord[chan]; in analyse_tex()
174 if (readmask & (1 << chan)) { in analyse_tex()
175 analyse_src(ctx, chan_info, &inst->Src[0].Register, chan); in analyse_tex()
207 unsigned chan; in analyse_sample() local
257 for (chan = 0; chan < 4; ++chan) { in analyse_sample()
258 struct lp_tgsi_channel_info *chan_info = &tex_info->coord[chan]; in analyse_sample()
[all …]
Dlp_bld_format_soa.c110 unsigned chan; in lp_build_format_swizzle_soa() local
111 for (chan = 0; chan < 4; ++chan) { in lp_build_format_swizzle_soa()
112 enum pipe_swizzle swizzle = format_desc->swizzle[chan]; in lp_build_format_swizzle_soa()
113 swizzled_out[chan] = lp_build_swizzle_soa_channel(bld, unswizzled, swizzle); in lp_build_format_swizzle_soa()
311 unsigned chan; in lp_build_unpack_rgba_soa() local
323 for (chan = 0; chan < format_desc->nr_channels; ++chan) { in lp_build_unpack_rgba_soa()
324 struct util_format_channel_description chan_desc = format_desc->channel[chan]; in lp_build_unpack_rgba_soa()
328 format_desc->swizzle[3] != chan) { in lp_build_unpack_rgba_soa()
332 inputs[chan] = lp_build_extract_soa_chan(&bld, in lp_build_unpack_rgba_soa()
362 unsigned chan; in lp_build_rgba8_to_fi32_soa() local
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/external/mesa3d/src/gallium/drivers/r600/sfn/
Dsfn_value.cpp47 Value::Value(Type type, uint32_t chan): in Value() argument
49 m_chan(chan) in Value()
66 void Value::set_chan(uint32_t chan) in set_chan() argument
68 m_chan = chan; in set_chan()
93 (sel() == lhs.sel() && chan() < lhs.chan()); in operator <()
97 LiteralValue::LiteralValue(float value, uint32_t chan): in LiteralValue() argument
98 Value(Value::literal, chan) in LiteralValue()
104 LiteralValue::LiteralValue(uint32_t value, uint32_t chan): in LiteralValue() argument
105 Value(Value::literal, chan) in LiteralValue()
110 LiteralValue::LiteralValue(int value, uint32_t chan): in LiteralValue() argument
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/external/tensorflow/tensorflow/lite/experimental/microfrontend/lib/
Dfilterbank_util.c112 int chan; in FilterbankPopulateState() local
113 for (chan = 0; chan < num_channels_plus_1; ++chan) { in FilterbankPopulateState()
116 while (FreqToMel((freq_index)*hz_per_sbin) <= center_mel_freqs[chan]) { in FilterbankPopulateState()
121 actual_channel_starts[chan] = chan_freq_index_start; in FilterbankPopulateState()
122 actual_channel_widths[chan] = width; in FilterbankPopulateState()
131 state->channel_frequency_starts[chan] = 0; in FilterbankPopulateState()
132 state->channel_weight_starts[chan] = 0; in FilterbankPopulateState()
133 state->channel_widths[chan] = kFilterbankChannelBlockSize; in FilterbankPopulateState()
137 for (j = 0; j < chan; ++j) { in FilterbankPopulateState()
152 state->channel_frequency_starts[chan] = aligned_start; in FilterbankPopulateState()
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/external/mesa3d/src/freedreno/ir3/
Dir3_nir_lower_load_barycentric_at_offset.c48 #define chan(var, c) nir_channel(b, var, c) in ir3_nir_lower_load_barycentric_at_offset_instr() macro
58 nir_fmul(b, chan(ij, 0), s), in ir3_nir_lower_load_barycentric_at_offset_instr()
59 nir_fmul(b, chan(ij, 1), s), in ir3_nir_lower_load_barycentric_at_offset_instr()
70 x = nir_ffma(b, chan(off, 0), chan(foo, 0), chan(sij, 0)); in ir3_nir_lower_load_barycentric_at_offset_instr()
71 y = nir_ffma(b, chan(off, 0), chan(foo, 1), chan(sij, 1)); in ir3_nir_lower_load_barycentric_at_offset_instr()
72 z = nir_ffma(b, chan(off, 0), chan(foo, 2), chan(sij, 2)); in ir3_nir_lower_load_barycentric_at_offset_instr()
74 x = nir_ffma(b, chan(off, 1), chan(bar, 0), x); in ir3_nir_lower_load_barycentric_at_offset_instr()
75 y = nir_ffma(b, chan(off, 1), chan(bar, 1), y); in ir3_nir_lower_load_barycentric_at_offset_instr()
76 z = nir_ffma(b, chan(off, 1), chan(bar, 2), z); in ir3_nir_lower_load_barycentric_at_offset_instr()
/external/wpa_supplicant_8/src/common/
Dieee802_11_common.c1089 static int ieee80211_chan_to_freq_us(u8 op_class, u8 chan) in ieee80211_chan_to_freq_us() argument
1095 if (chan < 1 || chan > 11) in ieee80211_chan_to_freq_us()
1097 return 2407 + 5 * chan; in ieee80211_chan_to_freq_us()
1104 if (chan < 36 || chan > 64) in ieee80211_chan_to_freq_us()
1106 return 5000 + 5 * chan; in ieee80211_chan_to_freq_us()
1109 if (chan < 100 || chan > 144) in ieee80211_chan_to_freq_us()
1111 return 5000 + 5 * chan; in ieee80211_chan_to_freq_us()
1117 if (chan < 149 || chan > 161) in ieee80211_chan_to_freq_us()
1119 return 5000 + 5 * chan; in ieee80211_chan_to_freq_us()
1121 if (chan < 149 || chan > 165) in ieee80211_chan_to_freq_us()
[all …]
/external/mesa3d/src/gallium/drivers/r600/sb/
Dsb_bc_finalize.cpp321 assert(fdst.chan() == slot || slot == SLOT_TRANS); in finalize_alu_group()
326 n->bc.dst_chan = d ? fdst.chan() : slot < SLOT_TRANS ? slot : 0; in finalize_alu_group()
387 src.chan = sc.chan(); in finalize_alu_src()
407 src.chan = gpr.chan(); in finalize_alu_src()
412 src.chan = v->gpr.chan(); in finalize_alu_src()
418 src.chan = 0; in finalize_alu_src()
432 src.chan = g->literal_chan(lv); in finalize_alu_src()
445 src.chan = k.chan(); in finalize_alu_src()
451 src.chan = 0; in finalize_alu_src()
454 src.chan = 0; in finalize_alu_src()
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/external/python/cpython3/Modules/
D_xxsubinterpretersmodule.c720 _PyChannelState *chan = PyMem_NEW(_PyChannelState, 1); in _channel_new() local
721 if (chan == NULL) { in _channel_new()
724 chan->mutex = PyThread_allocate_lock(); in _channel_new()
725 if (chan->mutex == NULL) { in _channel_new()
726 PyMem_Free(chan); in _channel_new()
731 chan->queue = _channelqueue_new(); in _channel_new()
732 if (chan->queue == NULL) { in _channel_new()
733 PyMem_Free(chan); in _channel_new()
736 chan->ends = _channelends_new(); in _channel_new()
737 if (chan->ends == NULL) { in _channel_new()
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/external/u-boot/drivers/ram/rockchip/
Dsdram_rk3399.c67 struct chan_info chan[2]; member
86 void (*modify_param)(const struct chan_info *chan,
214 static void *get_denali_ctl(const struct chan_info *chan, in get_denali_ctl() argument
217 return reg ? &chan->pctl->denali_ctl : &params->pctl_regs.denali_ctl; in get_denali_ctl()
220 static void *get_denali_phy(const struct chan_info *chan, in get_denali_phy() argument
223 return reg ? &chan->publ->denali_phy : &params->phy_regs.denali_phy; in get_denali_phy()
285 static void set_memory_map(const struct chan_info *chan, u32 channel, in set_memory_map() argument
289 u32 *denali_ctl = chan->pctl->denali_ctl; in set_memory_map()
290 u32 *denali_pi = chan->pi->denali_pi; in set_memory_map()
340 static int phy_io_config(const struct chan_info *chan, in phy_io_config() argument
[all …]
Dsdram_rk3188.c34 struct chan_info chan[1]; member
255 static void phy_cfg(const struct chan_info *chan, int channel, in phy_cfg() argument
258 struct rk3288_ddr_publ *publ = chan->publ; in phy_cfg()
259 struct rk3188_msch *msch = chan->msch; in phy_cfg()
376 static void set_bandwidth_ratio(const struct chan_info *chan, int channel, in set_bandwidth_ratio() argument
379 struct rk3288_ddr_pctl *pctl = chan->pctl; in set_bandwidth_ratio()
380 struct rk3288_ddr_publ *publ = chan->publ; in set_bandwidth_ratio()
381 struct rk3188_msch *msch = chan->msch; in set_bandwidth_ratio()
414 static int data_training(const struct chan_info *chan, int channel, in data_training() argument
422 struct rk3288_ddr_publ *publ = chan->publ; in data_training()
[all …]
/external/mesa3d/src/gallium/drivers/vc4/
Dvc4_nir_lower_io.c57 vc4_nir_unpack_8i(nir_builder *b, nir_ssa_def *src, unsigned chan) in vc4_nir_unpack_8i() argument
61 nir_imm_int(b, 8 * chan), in vc4_nir_unpack_8i()
67 vc4_nir_unpack_16i(nir_builder *b, nir_ssa_def *src, unsigned chan) in vc4_nir_unpack_16i() argument
71 nir_imm_int(b, 16 * chan), in vc4_nir_unpack_16i()
77 vc4_nir_unpack_16u(nir_builder *b, nir_ssa_def *src, unsigned chan) in vc4_nir_unpack_16u() argument
79 if (chan == 0) { in vc4_nir_unpack_16u()
87 vc4_nir_unpack_8f(nir_builder *b, nir_ssa_def *src, unsigned chan) in vc4_nir_unpack_8f() argument
89 return nir_channel(b, nir_unpack_unorm_4x8(b, src), chan); in vc4_nir_unpack_8f()
99 const struct util_format_channel_description *chan = in vc4_nir_get_vattr_channel_vpm() local
105 } else if (chan->size == 32 && chan->type == UTIL_FORMAT_TYPE_FLOAT) { in vc4_nir_get_vattr_channel_vpm()
[all …]
/external/mesa3d/src/gallium/drivers/panfrost/nir/
Dnir_lower_blend.c82 unsigned chan, in nir_alpha_saturate() argument
90 return (chan < 3) ? nir_fmin(b, Asrc, Adsti) : one; in nir_alpha_saturate()
99 unsigned chan, in nir_blend_factor_value() argument
107 return nir_channel(b, src, chan); in nir_blend_factor_value()
109 return nir_channel(b, src1, chan); in nir_blend_factor_value()
111 return nir_channel(b, dst, chan); in nir_blend_factor_value()
119 return nir_channel(b, bconst, chan); in nir_blend_factor_value()
123 return nir_alpha_saturate(b, src, dst, chan, half); in nir_blend_factor_value()
134 unsigned chan, in nir_blend_factor() argument
140 nir_blend_factor_value(b, src, src1, dst, bconst, chan, factor, half); in nir_blend_factor()
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