Searched refs:clk_pol (Results 1 – 5 of 5) sorted by relevance
| /external/arm-trusted-firmware/plat/intel/soc/common/drivers/qspi/ |
| D | cadence_qspi.h | 169 uint32_t clk_pol, uint32_t csda, uint32_t csdads,
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| D | cadence_qspi.c | 506 uint32_t clk_pol, uint32_t csda, uint32_t csdads, in cad_qspi_init() argument
522 status = cad_qspi_timing_config(clk_phase, clk_pol, csda, csdads, in cad_qspi_init()
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| /external/u-boot/drivers/video/imx/ |
| D | ipu.h | 196 unsigned clk_pol:1; /* true = rising edge */ member
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| D | mxc_ipuv3_fb.c | 258 sig_cfg.clk_pol = 1; in mxcfb_set_par()
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| D | ipu_disp.c | 1137 if (!sig.clk_pol) in ipu_init_sync_panel()
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