Home
last modified time | relevance | path

Searched refs:clock_set_target_val (Results 1 – 8 of 8) sorted by relevance

/external/u-boot/arch/arm/mach-imx/imx8m/
Dclock_imx8mm.c159 clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON | in dram_enable_bypass()
162 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | in dram_enable_bypass()
165 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | in dram_enable_bypass()
171 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | in dram_disable_bypass()
173 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | in dram_disable_bypass()
188 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON | in init_uart_clk()
194 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON | in init_uart_clk()
200 clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON | in init_uart_clk()
206 clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON | in init_uart_clk()
221 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | in init_wdog_clk()
[all …]
Dclock_imx8mq.c352 clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON | in mxs_set_lcdclk()
362 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | in init_wdog_clk()
364 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | in init_wdog_clk()
366 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | in init_wdog_clk()
381 clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON | in init_usb_clk()
384 clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON | in init_usb_clk()
387 clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON | in init_usb_clk()
399 clock_set_target_val(NAND_CLK_ROOT, in init_nand_clk()
411 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON | in init_uart_clk()
417 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON | in init_uart_clk()
[all …]
Dclock_slice.c620 int clock_set_target_val(enum clk_root_index clock_id, u32 val) in clock_set_target_val() function
/external/u-boot/arch/arm/mach-imx/mx7/
Dclock.c89 clock_set_target_val(USB_HSIC_CLK_ROOT, target); in enable_usboh3_clk()
540 clock_set_target_val(I2C1_CLK_ROOT + i2c_num, target); in enable_i2c_clk()
564 clock_set_target_val(USDHC1_CLK_ROOT, target); in init_clk_esdhc()
569 clock_set_target_val(USDHC2_CLK_ROOT, target); in init_clk_esdhc()
574 clock_set_target_val(USDHC3_CLK_ROOT, target); in init_clk_esdhc()
599 clock_set_target_val(UART1_CLK_ROOT, target); in init_clk_uart()
604 clock_set_target_val(UART2_CLK_ROOT, target); in init_clk_uart()
609 clock_set_target_val(UART3_CLK_ROOT, target); in init_clk_uart()
614 clock_set_target_val(UART4_CLK_ROOT, target); in init_clk_uart()
619 clock_set_target_val(UART5_CLK_ROOT, target); in init_clk_uart()
[all …]
Dclock_slice.c660 int clock_set_target_val(enum clk_root_index clock_id, u32 val) in clock_set_target_val() function
/external/u-boot/drivers/ddr/imx/imx8m/
Dddr_init.c41 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(4) | in ddr_init()
/external/u-boot/arch/arm/include/asm/arch-mx7/
Dclock_slice.h109 int clock_set_target_val(enum clk_root_index clock_id, u32 val);
/external/u-boot/arch/arm/include/asm/arch-imx8m/
Dclock.h265 int clock_set_target_val(enum clk_root_index clock_id, u32 val);