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Searched refs:cmp_instr (Results 1 – 3 of 3) sorted by relevance

/external/mesa3d/src/intel/compiler/
Dbrw_vec4_nir.cpp771 nir_alu_instr *cmp_instr = in optimize_predicate() local
774 switch (cmp_instr->op) { in optimize_predicate()
796 brw_swizzle_for_size(nir_op_infos[cmp_instr->op].input_sizes[0]); in optimize_predicate()
799 assert(nir_op_infos[cmp_instr->op].num_inputs == 2); in optimize_predicate()
801 nir_alu_type type = nir_op_infos[cmp_instr->op].input_types[i]; in optimize_predicate()
802 unsigned bit_size = nir_src_bit_size(cmp_instr->src[i].src); in optimize_predicate()
804 op[i] = get_nir_src(cmp_instr->src[i].src, type, 4); in optimize_predicate()
806 brw_swizzle_for_nir_swizzle(cmp_instr->src[i].swizzle); in optimize_predicate()
811 brw_cmod_for_nir_comparison(cmp_instr->op))); in optimize_predicate()
/external/v8/src/compiler/backend/s390/
Dcode-generator-s390.cc511 #define ASSEMBLE_COMPARE(cmp_instr, cmpl_instr) \ argument
520 __ cmp_instr(i.InputRegister(0), operand); \
526 __ cmp_instr(i.InputRegister(0), i.InputRegister(1)); \
532 __ cmp_instr(i.InputRegister(0), i.InputImmediate(1)); \
539 __ cmp_instr(i.InputRegister(0), i.InputStackSlot(1)); \
544 #define ASSEMBLE_COMPARE32(cmp_instr, cmpl_instr) \ argument
553 __ cmp_instr(i.InputRegister(0), operand); \
559 __ cmp_instr(i.InputRegister(0), i.InputRegister(1)); \
565 __ cmp_instr(i.InputRegister(0), i.InputImmediate(1)); \
572 __ cmp_instr(i.InputRegister(0), i.InputStackSlot32(1)); \
/external/v8/src/compiler/backend/ppc/
Dcode-generator-ppc.cc379 #define ASSEMBLE_COMPARE(cmp_instr, cmpl_instr) \ argument
386 __ cmp_instr(i.InputRegister(0), i.InputRegister(1), cr); \
392 __ cmp_instr##i(i.InputRegister(0), i.InputImmediate(1), cr); \
398 #define ASSEMBLE_FLOAT_COMPARE(cmp_instr) \ argument
401 __ cmp_instr(i.InputDoubleRegister(0), i.InputDoubleRegister(1), cr); \