| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| D | etnaviv_emit.h | 145 struct etna_coalesce *coalesce) in etna_coalesce_start() argument
147 coalesce->start = etna_cmd_stream_offset(stream); in etna_coalesce_start()
148 coalesce->last_reg = 0; in etna_coalesce_start()
149 coalesce->last_fixp = 0; in etna_coalesce_start()
154 struct etna_coalesce *coalesce) in etna_coalesce_end() argument
157 uint32_t size = end - coalesce->start; in etna_coalesce_end()
160 uint32_t offset = coalesce->start - 1; in etna_coalesce_end()
173 check_coalsence(struct etna_cmd_stream *stream, struct etna_coalesce *coalesce, in check_coalsence() argument
176 if (coalesce->last_reg != 0) { in check_coalsence()
177 if (((coalesce->last_reg + 4) != reg) || (coalesce->last_fixp != fixp)) { in check_coalsence()
[all …]
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| D | etnaviv_emit.c | 86 etna_coalsence_emit(stream, &coalesce, VIVS_##state_name, src_value)
89 etna_coalsence_emit_fixp(stream, &coalesce, VIVS_##state_name, src_value)
92 etna_coalsence_emit_reloc(stream, &coalesce, VIVS_##state_name, src_value)
130 struct etna_coalesce coalesce; in emit_halti5_only_state() local
132 etna_coalesce_start(stream, &coalesce); in emit_halti5_only_state()
155 etna_coalesce_end(stream, &coalesce); in emit_halti5_only_state()
164 struct etna_coalesce coalesce; in emit_pre_halti5_state() local
166 etna_coalesce_start(stream, &coalesce); in emit_pre_halti5_state()
210 etna_coalesce_end(stream, &coalesce); in emit_pre_halti5_state()
303 struct etna_coalesce coalesce; in etna_emit_state() local
[all …]
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| D | etnaviv_rs.c | 180 etna_coalsence_emit(stream, &coalesce, VIVS_##state_name, src_value)
183 etna_coalsence_emit_fixp(stream, &coalesce, VIVS_##state_name, src_value)
186 etna_coalsence_emit_reloc(stream, &coalesce, VIVS_##state_name, src_value)
196 struct etna_coalesce coalesce; in etna_submit_rs_state() local
206 etna_coalesce_start(stream, &coalesce); in etna_submit_rs_state()
210 etna_coalesce_end(stream, &coalesce); in etna_submit_rs_state()
213 etna_coalesce_start(stream, &coalesce); in etna_submit_rs_state()
230 etna_coalesce_end(stream, &coalesce); in etna_submit_rs_state()
233 etna_coalesce_start(stream, &coalesce); in etna_submit_rs_state()
261 etna_coalesce_end(stream, &coalesce); in etna_submit_rs_state()
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| D | etnaviv_texture_state.c | 276 etna_coalsence_emit(stream, &coalesce, VIVS_##state_name, src_value)
279 etna_coalsence_emit_fixp(stream, &coalesce, VIVS_##state_name, src_value)
282 etna_coalsence_emit_reloc(stream, &coalesce, VIVS_##state_name, src_value)
292 struct etna_coalesce coalesce; in etna_emit_texture_state() local
294 etna_coalesce_start(stream, &coalesce); in etna_emit_texture_state()
435 etna_coalesce_end(stream, &coalesce); in etna_emit_texture_state()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | regcoal-physreg.mir | 15 ; We usually should not coalesce copies from allocatable physregs.
21 ; It is fine to coalesce copies from reserved physregs
27 ; It is not fine to coalesce copies from reserved physregs when they are
35 ; Is is fine to coalesce copies from constant physregs even when they are
43 ; Is is fine to coalesce copies from constant physregs even when they are
56 ; Only coalesce when the source register is reserved as a whole (this is
64 ; It is not fine to coalesce copies from reserved physregs when they are
81 ; Cannot coalesce when there are reads of the physreg.
96 ; Cannot coalesce physreg because we have reads on other CFG paths (we
119 ; We can coalesce copies from physreg to vreg across multiple blocks.
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| /external/iw/ |
| D | coalesce.c | 17 SECTION(coalesce);
168 COMMAND(coalesce, enable, "<config-file>",
195 COMMAND(coalesce, disable, "", NL80211_CMD_SET_COALESCE, 0, CIB_PHY,
286 COMMAND(coalesce, show, "", NL80211_CMD_GET_COALESCE, 0, CIB_PHY, handle_coalesce_show,
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| D | Android.bp | 38 "coalesce.c",
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| /external/tensorflow/tensorflow/python/training/ |
| D | monitored_session.py | 158 coalesce = lambda a, b: a if a is not None else b function
159 init_op = coalesce(init_op, copy_from_scaffold.init_op)
160 init_feed_dict = coalesce(init_feed_dict,
163 … init_fn = coalesce(init_fn, copy_from_scaffold._user_init_fn) # pylint: disable=protected-access
164 ready_op = coalesce(ready_op, copy_from_scaffold.ready_op)
165 ready_for_local_init_op = coalesce(
167 local_init_op = coalesce(local_init_op, copy_from_scaffold.local_init_op)
168 local_init_feed_dict = coalesce(local_init_feed_dict,
170 summary_op = coalesce(summary_op, copy_from_scaffold.summary_op)
171 saver = coalesce(saver, copy_from_scaffold.saver)
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | 2012-10-04-AAPCS-byval-align8.ll | 32 ; ldm is not formed when the coalescer failed to coalesce everything.
59 ; ldm is not formed when the coalescer failed to coalesce everything.
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| /external/llvm/test/CodeGen/ARM/ |
| D | 2012-10-04-AAPCS-byval-align8.ll | 31 ; ldm is not formed when the coalescer failed to coalesce everything.
58 ; ldm is not formed when the coalescer failed to coalesce everything.
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| /external/ethtool/shell-completion/bash/ |
| D | ethtool | 227 # Completion for ethtool --coalesce
714 --coalesce
715 --show-coalesce
738 --coalesce)
739 # Remove --per-queue args to match normal --coalesce invocation
742 --coalesce
748 --show-coalesce)
1147 [--coalesce]=coalesce
1174 [--show-coalesce]=devname
1195 [-C]=coalesce
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | branch_coalesce.ll | 1 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs -enable-ppc-branch-coalesce…
2 …le=powerpc64-unknown-linux-gnu -verify-machineinstrs -enable-ppc-branch-coalesce < %s | FileCheck …
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| D | tls-store2.ll | 27 ; initial scheduling, but don't coalesce it again after we move the instructions
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | subreg-to-reg-3.ll | 5 ; Don't eliminate or coalesce away the explicit zero-extension!
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| D | subreg-to-reg-1.ll | 6 ; Don't eliminate or coalesce away the explicit zero-extension!
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| D | overlap-shift.ll | 2 ;; cannot coalesce it with Y. Because of this, a copy needs to be
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| D | cse-add-with-overflow.ll | 5 ; MachineCSE should coalesce trivial subregister copies.
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| /external/llvm/test/CodeGen/X86/ |
| D | subreg-to-reg-3.ll | 5 ; Don't eliminate or coalesce away the explicit zero-extension!
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| D | subreg-to-reg-1.ll | 6 ; Don't eliminate or coalesce away the explicit zero-extension!
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| D | overlap-shift.ll | 2 ;; cannot coalesce it with Y. Because of this, a copy needs to be
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| D | cse-add-with-overflow.ll | 5 ; MachineCSE should coalesce trivial subregister copies.
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| D | twoaddr-lea.ll | 2 ;; cannot coalesce it with Y. Because of this, a copy needs to be
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| /external/tensorflow/tensorflow/core/api_def/base_api/ |
| D | api_def_DecodeGif.pbtxt | 21 convert $src.gif -coalesce $dst.gif
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| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_util.cpp | 135 r->coalesce(&tail); in extend()
140 r->coalesce(&tail); in extend()
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | tls-store2.ll | 27 ; initial scheduling, but don't coalesce it again after we move the instructions
|