Home
last modified time | relevance | path

Searched refs:con1 (Results 1 – 25 of 37) sorted by relevance

12

/external/python/cpython2/Lib/sqlite3/test/
Dtransactions.py38 self.con1 = sqlite.connect(get_db_path(), timeout=0.1)
39 self.cur1 = self.con1.cursor()
46 self.con1.close()
74 self.con1.commit()
83 self.con1.commit()
92 self.con1.commit()
102 self.con1.isolation_level = None
103 self.assertEqual(self.con1.isolation_level, None)
108 self.con1.isolation_level = "DEFERRED"
109 self.assertEqual(self.con1.isolation_level , "DEFERRED")
[all …]
/external/python/cpython3/Lib/sqlite3/test/
Dtransactions.py37 self.con1 = sqlite.connect(get_db_path(), timeout=0.1)
38 self.cur1 = self.con1.cursor()
45 self.con1.close()
73 self.con1.commit()
82 self.con1.commit()
91 self.con1.commit()
101 self.con1.isolation_level = None
102 self.assertEqual(self.con1.isolation_level, None)
107 self.con1.isolation_level = "DEFERRED"
108 self.assertEqual(self.con1.isolation_level , "DEFERRED")
[all …]
Dhooks.py261 con1 = sqlite.connect(TESTFN, isolation_level=None)
263 con1.set_trace_callback(trace)
264 cur = con1.cursor()
/external/u-boot/drivers/adc/
Dexynos-adc.c49 cfg = readl(&regs->con1); in exynos_adc_start_channel()
50 writel(cfg | ADC_V2_CON1_STC_EN, &regs->con1); in exynos_adc_start_channel()
64 cfg = readl(&regs->con1); in exynos_adc_stop()
67 writel(cfg, &regs->con1); in exynos_adc_stop()
87 writel(ADC_V2_CON1_SOFT_RESET, &regs->con1); in exynos_adc_probe()
/external/u-boot/drivers/net/
Dpic32_eth.c66 writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_mii_init()
73 writel(ETHCON_ON, &ectl_p->con1.set); in pic32_mii_init()
241 writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_ctrl_reset()
248 writel(ETHCON_BUFCDEC, &ectl_p->con1.set); in pic32_ctrl_reset()
272 writel(ETHCON_ON, &ectl_p->con1.set); in pic32_ctrl_reset()
299 writel(ETHCON_BUFCDEC, &ectl_p->con1.set); in pic32_rx_desc_init()
321 writel(ETHCON_RXEN, &ectl_p->con1.set); in pic32_rx_desc_init()
358 if (readl(&ectl_p->con1.raw) & ETHCON_ON) in pic32_eth_stop()
365 writel(ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_eth_stop()
376 writel(ETHCON_ON, &ectl_p->con1.clr); in pic32_eth_stop()
[all …]
Dpic32_eth.h14 struct pic32_reg_atomic con1; /* 0x00 */ member
/external/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/
Dspm.c125 unsigned int con1; in spm_reset_and_init_pcm() local
141 con1 = mmio_read_32(SPM_PCM_CON1) & in spm_reset_and_init_pcm()
143 mmio_write_32(SPM_PCM_CON1, con1 | CON1_CFG_KEY | CON1_EVENT_LOCK_EN | in spm_reset_and_init_pcm()
272 unsigned int con1; in spm_kick_pcm_to_run() local
274 con1 = mmio_read_32(SPM_PCM_CON1) & in spm_kick_pcm_to_run()
277 mmio_write_32(SPM_PCM_CON1, CON1_CFG_KEY | con1); in spm_kick_pcm_to_run()
285 mmio_write_32(SPM_PCM_CON1, con1 | CON1_CFG_KEY | CON1_PCM_WDT_EN); in spm_kick_pcm_to_run()
/external/selinux/libsemanage/tests/
Dtest_iface.c297 semanage_context_t *con1 = NULL; in test_iface_get_set_ifcon() local
304 "my_user_u:my_role_r:my_type_t:s0", &con1) >= 0); in test_iface_get_set_ifcon()
307 CU_ASSERT(semanage_iface_set_ifcon(sh, iface, con1) == 0); in test_iface_get_set_ifcon()
309 CU_ASSERT_CONTEXT_EQUAL(con1, con2); in test_iface_get_set_ifcon()
320 semanage_context_t *con1 = NULL; in test_iface_get_set_msgcon() local
327 "my_user_u:my_role_r:my_type_t:s0", &con1) >= 0); in test_iface_get_set_msgcon()
330 CU_ASSERT(semanage_iface_set_msgcon(sh, iface, con1) == 0); in test_iface_get_set_msgcon()
332 CU_ASSERT_CONTEXT_EQUAL(con1, con2); in test_iface_get_set_msgcon()
Dtest_port.c384 semanage_context_t *con1 = NULL; in test_port_get_set_con() local
391 con1 = semanage_port_get_con(port_tmp); in test_port_get_set_con()
394 CU_ASSERT(semanage_port_set_con(sh, port, con1) >= 0); in test_port_get_set_con()
396 CU_ASSERT_CONTEXT_EQUAL(con1, con2); in test_port_get_set_con()
802 semanage_context_t *con1 = NULL; in helper_port_validate_local_twoports() local
818 "system_u:object_r:user_home_t:s0", &con1) >= 0); in helper_port_validate_local_twoports()
822 semanage_port_set_con(sh, port1, con1); in helper_port_validate_local_twoports()
850 semanage_context_t *con1 = NULL; in helper_port_validate_local_proto() local
874 "system_u:object_r:user_home_t:s0", &con1) >= 0); in helper_port_validate_local_proto()
880 semanage_port_set_con(sh, port1, con1); in helper_port_validate_local_proto()
Dtest_node.c424 semanage_context_t *con1 = NULL; in test_node_get_set_con() local
431 "my_user_u:my_role_r:my_type_t:s0", &con1) >= 0); in test_node_get_set_con()
434 CU_ASSERT(semanage_node_set_con(sh, node, con1) == 0); in test_node_get_set_con()
436 CU_ASSERT_CONTEXT_EQUAL(con1, con2); in test_node_get_set_con()
/external/u-boot/drivers/clk/exynos/
Dclk-pll.c19 unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq) in pll145x_get_rate() argument
21 unsigned long pll_con1 = readl(con1); in pll145x_get_rate()
Dclk-pll.h8 unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);
/external/u-boot/drivers/clk/rockchip/
Dclk_rk322x.c58 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
60 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
65 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
70 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
73 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkclk_set_pll()
201 con = readl(&pll->con1); in rkclk_pll_get_rate()
Dclk_rk3128.c55 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
57 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
62 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
67 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
70 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkclk_set_pll()
268 con = readl(&pll->con1); in rkclk_pll_get_rate()
Dclk_rv1108.c94 rk_clrsetreg(&pll->con1, POSTDIV1_MASK | POSTDIV2_MASK | REFDIV_MASK, in rkclk_set_pll()
121 uint32_t con0, con1, con3; in rkclk_pll_get_rate() local
130 con1 = readl(&pll->con1); in rkclk_pll_get_rate()
132 postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT; in rkclk_pll_get_rate()
133 postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT; in rkclk_pll_get_rate()
134 refdiv = (con1 >> REFDIV_SHIFT) & REFDIV_MASK; in rkclk_pll_get_rate()
Dclk_rk3036.c62 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
67 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
72 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkclk_set_pll()
200 con = readl(&pll->con1); in rkclk_pll_get_rate()
Dclk_rk3368.c77 con = readl(&pll->con1); in rkclk_pll_get_rate()
106 writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1); in rkclk_set_pll()
119 while (!(readl(&pll->con1) & PLL_LOCK_STA)) in rkclk_set_pll()
/external/u-boot/arch/arm/mach-exynos/include/mach/
Dadc.h58 unsigned int con1; member
/external/u-boot/arch/arm/include/asm/arch-rockchip/
Dcru_rk3188.h36 u32 con1; member
Dcru_rk3368.h26 unsigned int con1; member
Dcru_rk3036.h35 unsigned int con1; member
Dcru_rk322x.h36 unsigned int con1; member
Dcru_rk3128.h36 unsigned int con1; member
Dcru_rk3288.h37 u32 con1; member
/external/u-boot/arch/arm/mach-rockchip/rk3036/
Dsdram_rk3036.c335 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkdclk_init()
341 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkdclk_init()
346 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkdclk_init()

12