| /external/slf4j/slf4j-migrator/src/main/java/org/slf4j/migrator/line/ |
| D | JCLRuleSet.java | 55 …SingleConversionRule cr5 = new SingleConversionRule(Pattern.compile("LogFactory.getLog\\("), "Logg… in JCLRuleSet() local
63 conversionRuleList.add(cr5); in JCLRuleSet()
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | cc.ll | 11 …call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{cr0},~{cr1},~{cr2},~{cr3},~{cr4},~{cr5}…
44 …call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{cc},~{cr1},~{cr2},~{cr3},~{cr4},~{cr5},…
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| D | addisdtprelha-nonr3.mir | 63 … %ctr8, implicit-def dead %cr0, implicit-def dead %cr1, implicit-def dead %cr5, implicit-def dead …
67 … %ctr8, implicit-def dead %cr0, implicit-def dead %cr1, implicit-def dead %cr5, implicit-def dead …
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | cc.ll | 11 …call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{cr0},~{cr1},~{cr2},~{cr3},~{cr4},~{cr5}…
44 …call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{cc},~{cr1},~{cr2},~{cr3},~{cr4},~{cr5},…
|
| D | addisdtprelha-nonr3.mir | 59 … $ctr8, implicit-def dead $cr0, implicit-def dead $cr1, implicit-def dead $cr5, implicit-def dead …
63 … $ctr8, implicit-def dead $cr0, implicit-def dead $cr1, implicit-def dead $cr5, implicit-def dead …
|
| D | expand-foldable-isel.ll | 27 ; CHECK-GEN-ISEL-TRUE: isel r29, r5, r6, 4*cr5+lt
32 ; CHECK: bc 12, 4*cr5+lt, .LBB0_3
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| D | tls_get_addr_fence2.mir | 56 … $ctr8, implicit-def dead $cr0, implicit-def dead $cr1, implicit-def dead $cr5, implicit-def dead …
|
| D | tls_get_addr_fence1.mir | 55 … $ctr8, implicit-def dead $cr0, implicit-def dead $cr1, implicit-def dead $cr5, implicit-def dead …
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/ |
| D | ppc64-regs.s | 82 #CHECK: .cfi_offset cr5, 625
198 .cfi_offset cr5,625
|
| D | ppc64-encoding-ext.s | 24 beqlr cr5
109 btlr 4*cr5+lt
112 btlr 4*cr5+gt
115 btlr 4*cr5+eq
118 btlr 4*cr5+so
121 btlr 4*cr5+un
|
| /external/llvm/test/MC/PowerPC/ |
| D | ppc64-regs.s | 82 #CHECK: .cfi_offset cr5, 625
198 .cfi_offset cr5,625
|
| D | ppc64-encoding-ext.s | 24 beqlr cr5
109 btlr 4*cr5+lt
112 btlr 4*cr5+gt
115 btlr 4*cr5+eq
118 btlr 4*cr5+so
121 btlr 4*cr5+un
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | ipra-reg-usage.ll | 6 …p $ip $rip $riz $ss $ssp $bnd0 $bnd1 $bnd2 $bnd3 $cr0 $cr1 $cr2 $cr3 $cr4 $cr5 $cr6 $cr7 $cr8 $cr9…
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| /external/v8/src/codegen/s390/ |
| D | register-s390.h | 35 V(cr0) V(cr1) V(cr2) V(cr3) V(cr4) V(cr5) V(cr6) V(cr7) \
|
| /external/v8/src/codegen/ppc/ |
| D | register-ppc.h | 56 V(cr0) V(cr1) V(cr2) V(cr3) V(cr4) V(cr5) V(cr6) V(cr7) \
|
| /external/v8/src/codegen/arm/ |
| D | register-arm.h | 55 V(cr0) V(cr1) V(cr2) V(cr3) V(cr4) V(cr5) V(cr6) V(cr7) \
|
| D | assembler-arm.cc | 2285 mcr(p15, 0, r0, cr7, cr5, 4); in isb()
|
| /external/libunwind_llvm/src/ |
| D | UnwindRegistersRestore.S | 718 ldcl p1, cr5, [r0], #8 @ wldrd wR5, [r0], #8
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.td | 199 def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73, 73]>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.td | 207 def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73, 73]>;
|
| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.td | 289 def CR5 : X86Reg<"cr5", 5>;
|
| /external/elfutils/tests/ |
| D | testfile44.expect.bz2 | |
| D | testfile45.expect.bz2 | 1testfile45.o: elf64-elf_x86_64
2
3Disassembly of section .text:
4
5 0 ... |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.td | 338 def CR5 : X86Reg<"cr5", 5>;
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| D | X86GenAsmMatcher.inc | 186 return 74; // "cr5"
|