/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
D | cond-sel.ll | 107 ; CHECK: csinv {{w[0-9]+}}, [[LHS]], [[RHS]], ls 115 ; CHECK: csinv {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le 124 ; CHECK: csinv {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls 132 ; CHECK: csinv {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le 152 ; CHECK: csinv {{w[0-9]+}}, [[RHS2]], wzr, gt 160 ; CHECK: csinv {{x[0-9]+}}, [[RHS3]], xzr, hi
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D | cond-sel-value-prop.ll | 67 ; CHECK: csinv x0, x[[REG]], xzr, ne 94 ; CHECK: csinv x0, x[[REG]], xzr, eq 105 ; CHECK: csinv w0, w[[REG]], wzr, eq
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D | arm64-early-ifcvt.ll | 114 ; CHECK-NEXT: csinv w0, w1, w0, eq 132 ; CHECK-NEXT: csinv x0, x1, x0, eq 150 ; CHECK-NEXT: csinv w0, w1, w0, ne 168 ; CHECK-NEXT: csinv x0, x1, x0, ne
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D | win64_vararg.ll | 130 ; CHECK: csinv w0, w0, wzr, ge 237 ; CHECK: csinv w0, w0, wzr, ge
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D | arm64-csel.ll | 105 ; CHECK: csinv w0, w1, w2, ne
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/external/llvm/test/CodeGen/AArch64/ |
D | cond-sel.ll | 107 ; CHECK: csinv {{w[0-9]+}}, [[LHS]], [[RHS]], ls 115 ; CHECK: csinv {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le 124 ; CHECK: csinv {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls 132 ; CHECK: csinv {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le 152 ; CHECK: csinv {{w[0-9]+}}, [[RHS2]], wzr, gt 160 ; CHECK: csinv {{x[0-9]+}}, [[RHS3]], xzr, hi
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D | fp16-v4-instructions.ll | 303 ; CHECK-DAG: csinv {{.*}}, [[REG1]], wzr, vc 304 ; CHECK-DAG: csinv {{.*}}, [[REG2]], wzr, vc 305 ; CHECK-DAG: csinv {{.*}}, [[REG3]], wzr, vc 306 ; CHECK-DAG: csinv {{.*}}, [[REG4]], wzr, vc 421 ; CHECK-DAG: csinv {{.*}}, [[REG1]], wzr, le 422 ; CHECK-DAG: csinv {{.*}}, [[REG2]], wzr, le 423 ; CHECK-DAG: csinv {{.*}}, [[REG3]], wzr, le 424 ; CHECK-DAG: csinv {{.*}}, [[REG4]], wzr, le
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D | arm64-early-ifcvt.ll | 114 ; CHECK-NEXT: csinv w0, w1, w0, eq 132 ; CHECK-NEXT: csinv x0, x1, x0, eq 150 ; CHECK-NEXT: csinv w0, w1, w0, ne 168 ; CHECK-NEXT: csinv x0, x1, x0, ne
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D | arm64-csel.ll | 104 ; CHECK: csinv w0, w1, w2, ne
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/external/capstone/suite/MC/AArch64/ |
D | basic-a64-instructions.s.cs | 516 0x01,0x10,0x93,0x5a = csinv w1, w0, w19, ne 517 0xbf,0x00,0x89,0x5a = csinv wzr, w5, w9, eq 518 0xe9,0xc3,0x9e,0x5a = csinv w9, wzr, w30, gt 519 0x81,0x43,0x9f,0x5a = csinv w1, w28, wzr, mi 520 0xf3,0xb2,0x9d,0xda = csinv x19, x23, x29, lt 521 0x7f,0xa0,0x84,0xda = csinv xzr, x3, x4, ge 522 0xe5,0x23,0x86,0xda = csinv x5, xzr, x6, hs 523 0x07,0x31,0x9f,0xda = csinv x7, x8, xzr, lo 534 0xf4,0x03,0x9f,0x5a = csinv w20, wzr, wzr, eq 535 0xfe,0xb3,0x9f,0xda = csinv x30, xzr, xzr, lt [all …]
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/external/arm-optimized-routines/string/aarch64/ |
D | strnlen.S | 151 csinv data1, data1, xzr, le
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D | strncmp.S | 72 csinv endloop, diff, xzr, pl /* Last Dword or differences. */
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D | strcpy.S | 264 csinv data1, data1, xzr, lt
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
D | basic-a64-instructions.s | 1365 csinv w1, w0, w19, ne 1366 csinv wzr, w5, w9, eq 1367 csinv w9, wzr, w30, gt 1368 csinv w1, w28, wzr, mi 1374 csinv x19, x23, x29, lt 1375 csinv xzr, x3, x4, ge 1376 csinv x5, xzr, x6, cs 1377 csinv x7, x8, xzr, cc
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D | arm64-arithmetic-encoding.s | 554 csinv w1, w2, w3, eq 555 csinv x1, x2, x3, eq
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D | basic-a64-diagnostics.s | 1371 csinv w20, wsp, wsp, mi 1372 csinv sp, x30, x29, le
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/external/llvm/test/MC/AArch64/ |
D | basic-a64-instructions.s | 1365 csinv w1, w0, w19, ne 1366 csinv wzr, w5, w9, eq 1367 csinv w9, wzr, w30, gt 1368 csinv w1, w28, wzr, mi 1374 csinv x19, x23, x29, lt 1375 csinv xzr, x3, x4, ge 1376 csinv x5, xzr, x6, cs 1377 csinv x7, x8, xzr, cc
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D | arm64-arithmetic-encoding.s | 554 csinv w1, w2, w3, eq 555 csinv x1, x2, x3, eq
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D | basic-a64-diagnostics.s | 1366 csinv w20, wsp, wsp, mi 1367 csinv sp, x30, x29, le
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
D | arm64-arithmetic.txt | 520 # CHECK: csinv w1, w2, w3, eq 522 # CHECK: csinv x1, x2, x3, eq
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D | basic-a64-instructions.txt | 912 # CHECK: csinv w1, w0, w19, ne 913 # CHECK: csinv wzr, w5, w9, eq 914 # CHECK: csinv w9, wzr, w30, gt 915 # CHECK: csinv w1, w28, wzr, mi 916 # CHECK: csinv x19, x23, x29, lt 917 # CHECK: csinv xzr, x3, x4, ge 918 # CHECK: csinv x5, xzr, x6, hs 919 # CHECK: csinv x7, x8, xzr, lo 952 # CHECK: csinv x3, xzr, xzr, nv 985 # CHECK: csinv x1, x0, x0, al [all …]
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/external/llvm/test/MC/Disassembler/AArch64/ |
D | arm64-arithmetic.txt | 520 # CHECK: csinv w1, w2, w3, eq 522 # CHECK: csinv x1, x2, x3, eq
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D | basic-a64-instructions.txt | 911 # CHECK: csinv w1, w0, w19, ne 912 # CHECK: csinv wzr, w5, w9, eq 913 # CHECK: csinv w9, wzr, w30, gt 914 # CHECK: csinv w1, w28, wzr, mi 915 # CHECK: csinv x19, x23, x29, lt 916 # CHECK: csinv xzr, x3, x4, ge 917 # CHECK: csinv x5, xzr, x6, hs 918 # CHECK: csinv x7, x8, xzr, lo 951 # CHECK: csinv x3, xzr, xzr, nv 984 # CHECK: csinv x1, x0, x0, al [all …]
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/external/vixl/test/aarch64/ |
D | test-disasm-aarch64.cc | 2156 COMPARE(csinv(w12, w13, w14, mi), "csinv w12, w13, w14, mi"); in TEST() 2157 COMPARE(csinv(x15, x16, x17, pl), "csinv x15, x16, x17, pl"); in TEST() 2175 COMPARE(csinv(x4, x5, x6, al), "csinv x4, x5, x6, al"); in TEST() 2176 COMPARE(csinv(x5, x6, x7, nv), "csinv x5, x6, x7, nv"); in TEST()
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/external/v8/src/codegen/arm64/ |
D | macro-assembler-arm64-inl.h | 483 csinv(rd, rn, rm, cond); in Csinv()
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