Searched refs:cwl (Results 1 – 11 of 11) sorted by relevance
26 unsigned int cwl; in mv_ddr_cwl_calc() local29 cwl = 9; in mv_ddr_cwl_calc()31 cwl = 10; in mv_ddr_cwl_calc()33 cwl = 11; in mv_ddr_cwl_calc()35 cwl = 12; in mv_ddr_cwl_calc()37 cwl = 14; in mv_ddr_cwl_calc()39 cwl = 16; in mv_ddr_cwl_calc()41 cwl = 0; in mv_ddr_cwl_calc()43 return cwl; in mv_ddr_cwl_calc()
233 pdram_timing->cwl = 6; in ddr3_get_parameter()236 pdram_timing->cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0xf; in ddr3_get_parameter()268 pdram_timing->mr[2] = DDR3_MR2_CWL(pdram_timing->cwl); in ddr3_get_parameter()348 pdram_timing->todton = pdram_timing->cwl - 2; in ddr3_get_parameter()438 pdram_timing->cwl = 2; in lpddr2_get_parameter()442 pdram_timing->cwl = 2; in lpddr2_get_parameter()446 pdram_timing->cwl = 3; in lpddr2_get_parameter()450 pdram_timing->cwl = 4; in lpddr2_get_parameter()454 pdram_timing->cwl = 4; in lpddr2_get_parameter()680 pdram_timing->cwl = 3; in lpddr3_get_parameter()[all …]
224 uint32_t cwl; member285 static uint32_t get_wrlat_adj(uint32_t dram_type, uint32_t cwl) in get_wrlat_adj() argument303 if (cwl == p[i].cwl) in get_wrlat_adj()532 (pdram_timing->cwl << 24)); in gen_rk3399_ctl_params_f0()654 (get_wrlat_adj(timing_config->dram_type, pdram_timing->cwl) in gen_rk3399_ctl_params_f0()684 tmp = pdram_timing->cl - pdram_timing->cwl; in gen_rk3399_ctl_params_f0()784 (pdram_timing->cwl << 16)); in gen_rk3399_ctl_params_f1()903 pdram_timing->cwl) << 8) | in gen_rk3399_ctl_params_f1()934 tmp = pdram_timing->cl - pdram_timing->cwl; in gen_rk3399_ctl_params_f1()1100 tmp = pdram_timing->cl - pdram_timing->cwl; in gen_rk3399_pi_params_f0()[all …]
169 uint32_t cwl; member
576 u32 reg, tmp, cwl; local1089 cwl = 5; /* CWL = 5 */1091 cwl = 6; /* CWL = 6 */1093 cwl = 7; /* CWL = 7 */1095 cwl = 8; /* CWL = 8 */1097 cwl = 9; /* CWL = 9 */1099 cwl = 10; /* CWL = 10 */1101 cwl = 11; /* CWL = 11 */1103 cwl = 12; /* CWL = 12 */1105 cwl = 12; /* CWL = 12 */[all …]
998 reg |= (((dram_info->cwl) & REG_DFS_CWL_NEXT_STATE_MASK) << in ddr3_dfs_low_2_high()1184 reg |= ((dram_info->cwl) << REG_DDR3_MR2_CWL_OFFS); in ddr3_dfs_low_2_high()1496 reg |= dram_info->cwl << REG_DDR3_MR2_CWL_OFFS; in ddr3_dfs_low_2_high()
268 u32 cwl; member
145 dram_info.cwl = reg; in ddr3_hw_training()
122 u32 cwl; member253 spd->cwl = 0; in ddrtimingcalculation()255 spd->cwl = 1; in ddrtimingcalculation()257 spd->cwl = 2; in ddrtimingcalculation()259 spd->cwl = 3; in ddrtimingcalculation()261 spd->cwl = 4; in ddrtimingcalculation()263 spd->cwl = 5; in ddrtimingcalculation()356 (spd->cwl & 7) << 3 | (spd->pasr & 7); in init_ddr3param()370 (DYN_ODT & 3) << 22 | (spd->cwl & 0x7) << 14 | in init_ddr3param()
86 unsigned int cwl; in compute_cas_write_latency() local89 cwl = 9; in compute_cas_write_latency()91 cwl = 10; in compute_cas_write_latency()93 cwl = 11; in compute_cas_write_latency()95 cwl = 12; in compute_cas_write_latency()97 cwl = 14; in compute_cas_write_latency()99 cwl = 16; in compute_cas_write_latency()101 cwl = 18; in compute_cas_write_latency()103 return cwl; in compute_cas_write_latency()120 unsigned int cwl; in compute_cas_write_latency() local[all …]
262 uint8_t cwl; in ddrphy_init() local267 cwl = 5 + mrc_params->ddr_speed; in ddrphy_init()430 ((cwl - 2) << 0), 0x003f1f1f); in ddrphy_init()436 ((cwl - 2) << 0), 0x003f1f1f); in ddrphy_init()