Home
last modified time | relevance | path

Searched refs:cycles (Results 1 – 25 of 466) sorted by relevance

12345678910>>...19

/external/chromium-trace/catapult/systrace/systrace/test_data/
Dprofile-chrome_systrace_perf_chrome_data1 …cycles:HG", "weight": 297850, "ts": 196493621870.241, "cpu": 2, "comm": "ksoftirqd/2", "tid": 1410…
/external/tensorflow/tensorflow/python/saved_model/
Dload_test.py75 def cycle(obj, cycles, signatures=None): argument
79 for _ in range(cycles):
92 dict(testcase_name="ReloadOnce", cycles=1),
93 dict(testcase_name="ReloadTwice", cycles=2),
94 dict(testcase_name="ReloadThrice", cycles=3))
97 def test_structure_import(self, cycles): argument
103 imported = cycle(root, cycles)
107 def test_variables(self, cycles): argument
111 imported = cycle(root, cycles)
117 def test_variables_name(self, cycles): argument
[all …]
/external/u-boot/drivers/ram/k3-j721e/
Dlpddr4.c1231 lpddr4_ctlregs * ctlregbase, uint32_t * cycles) in readpdwakeup() argument
1236 *cycles = in readpdwakeup()
1242 *cycles = in readpdwakeup()
1249 *cycles = in readpdwakeup()
1258 lpddr4_ctlregs * ctlregbase, uint32_t * cycles) in readsrshortwakeup() argument
1263 *cycles = in readsrshortwakeup()
1269 *cycles = in readsrshortwakeup()
1276 *cycles = in readsrshortwakeup()
1285 lpddr4_ctlregs * ctlregbase, uint32_t * cycles) in readsrlongwakeup() argument
1290 *cycles = in readsrlongwakeup()
[all …]
/external/tensorflow/tensorflow/compiler/xla/service/
Dhuman_readable_profile_builder.cc45 if (op.optimal_seconds == 0 && op.cycles == 0) { in ToString()
51 if (op.cycles > 0 && op.bytes_accessed >= 0) { in ToString()
53 HumanReadableNumBytes(op.bytes_accessed / CyclesToSeconds(op.cycles)), in ToString()
55 double bpc = static_cast<double>(op.bytes_accessed) / op.cycles; in ToString()
56 if (op.bytes_accessed > op.cycles) { in ToString()
66 cumulative_cycles += op.cycles; in ToString()
69 cycles_percent = op.cycles / static_cast<double>(total_cycles_) * 100; in ToString()
84 double nsecs = op.cycles / clock_rate_ghz_; in ToString()
89 op.cycles, cycles_percent_str, CyclesToMicroseconds(op.cycles), in ToString()
115 std::min(double{op.optimal_seconds}, CyclesToSeconds(op.cycles)); in ToString()
[all …]
Dhuman_readable_profile_builder.h49 absl::string_view category, int64 cycles, int64 flop_count, in AddOp() argument
53 cycles, flop_count, transcendental_count, in AddOp()
65 int64 cycles; member
72 double CyclesToSeconds(int64 cycles) const { in CyclesToSeconds() argument
73 return cycles / clock_rate_ghz_ / 1e9; in CyclesToSeconds()
75 double CyclesToMicroseconds(int64 cycles) const { in CyclesToMicroseconds() argument
76 return cycles / clock_rate_ghz_ / 1000.0; in CyclesToMicroseconds()
/external/igt-gpu-tools/tests/i915/
Dgem_sync.c109 unsigned long cycles; in sync_ring() local
123 cycles = 0; in sync_ring()
128 } while (++cycles & 1023); in sync_ring()
133 cycles, elapsed*1e6/cycles); in sync_ring()
148 unsigned long cycles; in idle_ring() local
165 cycles = 0; in idle_ring()
170 } while (++cycles & 1023); in idle_ring()
175 cycles, elapsed*1e6/cycles); in idle_ring()
211 unsigned long cycles; in wakeup_ring() local
237 cycles = 0; in wakeup_ring()
[all …]
/external/u-boot/cmd/
Dtime.c9 static void report_time(ulong cycles) in report_time() argument
14 total_seconds = cycles / CONFIG_SYS_HZ; in report_time()
15 remainder = cycles % CONFIG_SYS_HZ; in report_time()
29 ulong cycles = 0; in do_time() local
36 retval = cmd_process(0, argc - 1, argv + 1, &repeatable, &cycles); in do_time()
37 report_time(cycles); in do_time()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMScheduleA9.td82 // No operand cycles
203 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
347 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
469 // Extra latency cycles since wbck is 2 cycles
478 // Extra latency cycles since wbck is 2 cycles
488 // Extra latency cycles since wbck is 4 cycles
497 // Extra latency cycles since wbck is 4 cycles
669 // Extra 1 latency cycle since wbck is 2 cycles
678 // Extra 1 latency cycle since wbck is 2 cycles
719 // FIXME: assumes 2 doubles which requires 2 LS cycles.
[all …]
/external/llvm/lib/Target/ARM/
DARMScheduleA9.td82 // No operand cycles
203 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
347 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
469 // Extra latency cycles since wbck is 2 cycles
478 // Extra latency cycles since wbck is 2 cycles
488 // Extra latency cycles since wbck is 4 cycles
497 // Extra latency cycles since wbck is 4 cycles
669 // Extra 1 latency cycle since wbck is 2 cycles
678 // Extra 1 latency cycle since wbck is 2 cycles
719 // FIXME: assumes 2 doubles which requires 2 LS cycles.
[all …]
/external/antlr/tool/src/main/java/org/antlr/tool/
DLeftRecursionCyclesMessage.java39 public Collection<? extends Collection<? extends Rule>> cycles; field in LeftRecursionCyclesMessage
41 public LeftRecursionCyclesMessage(Collection<? extends Collection<? extends Rule>> cycles) { in LeftRecursionCyclesMessage() argument
43 this.cycles = cycles; in LeftRecursionCyclesMessage()
49 st.add("listOfCycles", cycles); in toString()
/external/autotest/client/cros/
Dstorage.py273 storages = self.wait_for_devices(filter_dict, cycles=1,
291 def wait_for_devices(self, storage_filter, time_to_sleep=1, cycles=10, argument
309 '%d secs' % (storage_filter, cycles, time_to_sleep))
315 if cycles == -1:
320 while cycles == -1 or cycle < cycles:
338 (storage_filter, time_to_sleep*cycles))
342 def wait_for_device(self, storage_filter, time_to_sleep=1, cycles=10, argument
367 cycles=cycles,
/external/boringssl/ios-arm/crypto/fipsmodule/
Dsha256-armv4.S35 @ lute" terms is ~2250 cycles per 64-byte block or ~35 cycles per
41 @ Cortex A8 core and ~20 cycles per processed byte.
46 @ improvement on Cortex A8 core and ~15.4 cycles per processed byte.
51 @ byte in 12.5 cycles or 23% faster than integer-only code. Snapdragon
52 @ S4 does it in 12.5 cycles too, but it's 50% faster than integer-only
Dsha512-armv4.S35 @ by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue
41 @ Cortex A8 core and ~40 cycles per processed byte.
46 @ improvement on Coxtex A8 core and ~38 cycles per byte.
51 @ one byte in 23.3 cycles or ~60% faster than integer-only code.
/external/boringssl/linux-arm/crypto/fipsmodule/
Dsha256-armv4.S36 @ lute" terms is ~2250 cycles per 64-byte block or ~35 cycles per
42 @ Cortex A8 core and ~20 cycles per processed byte.
47 @ improvement on Cortex A8 core and ~15.4 cycles per processed byte.
52 @ byte in 12.5 cycles or 23% faster than integer-only code. Snapdragon
53 @ S4 does it in 12.5 cycles too, but it's 50% faster than integer-only
Dsha512-armv4.S36 @ by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue
42 @ Cortex A8 core and ~40 cycles per processed byte.
47 @ improvement on Coxtex A8 core and ~38 cycles per byte.
52 @ one byte in 23.3 cycles or ~60% faster than integer-only code.
/external/autotest/client/tests/signaltest/src/
Dsignaltest.c54 unsigned long cycles; member
154 if (!par->id && !(stat->cycles & 0x0F)) in signalthread()
185 stat->cycles++; in signalthread()
188 stat->values[stat->cycles & par->bufmsk] = diff; in signalthread()
190 if (par->max_cycles && par->max_cycles == stat->cycles) in signalthread()
300 stat->cycles, stat->min, stat->act, in print_stat()
301 stat->cycles ? in print_stat()
302 (long)(stat->avg/stat->cycles) : 0, stat->max); in print_stat()
305 while (stat->cycles != stat->cyclesread) { in print_stat()
398 if(max_cycles && stat[0].cycles >= max_cycles) in main()
/external/u-boot/arch/xtensa/lib/
Dtime.c25 static void delay_cycles(unsigned cycles) in delay_cycles() argument
28 unsigned expiry = get_ccount() + cycles; in delay_cycles()
40 for (i = cycles >> 4U; i > 0; --i) in delay_cycles()
42 fake_ccount += cycles; in delay_cycles()
/external/u-boot/board/keymile/km_arm/
Dkwbimage_256M8_1.cfg118 DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1)
119 # bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles
120 # bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles
121 # bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles
122 # bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles
123 # bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles
126 # bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles
127 # bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles
130 # bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles
196 # bit 7-4: 2, M_ODT assertion 2 cycles after read start command
[all …]
/external/tensorflow/tensorflow/compiler/xla/tests/
Dxla_hlo_profile_test.cc46 int64 cycles; member
109 line, regexp_pattern, &parsed_line.cycles, &parsed_line.cycles_percentage,
247 EXPECT_GT(total_profile.cycles, 0); in XLA_TEST_F()
253 EXPECT_GT(total_profile.cycles, dot_profile.cycles); in XLA_TEST_F()
260 EXPECT_GT(total_profile.cycles, tanh_profile.cycles); in XLA_TEST_F()
352 EXPECT_GT(total_while_body_profile.cycles, 0); in XLA_TEST_F()
356 EXPECT_GT(total_while_body_profile.cycles, multiply_profile.cycles); in XLA_TEST_F()
/external/webrtc/webrtc/modules/audio_coding/neteq/tools/
Drtp_analyze.cc106 int cycles = -1; in main() local
132 if (cycles == -1) { in main()
135 cycles = 0; in main()
148 cycles++; in main()
157 64.0 * cycles; in main()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCScheduleP9.td22 // Load latency is 4 or 5 cycles depending on the load. This latency assumes
24 // There are two instructions (lxvl, lxvll) that have a latencty of 6 cycles.
26 // of instructions are 4 or 5 cycles.
29 // A total of 16 cycles to recover from a branch mispredict.
144 // An ALU may take either 2 or 3 cycles to complete the operation.
172 // A DIV unit may take from 5 to 40 cycles to complete.
173 // Some DIV operations may keep the unit busy for up to 8 cycles.
198 // A DP unit may take from 2 to 36 cycles to complete.
199 // Some DP operations keep the unit busy for up to 10 cycles.
297 // Loads can have 4, 5 or 6 cycles of latency.
[all …]
/external/snakeyaml/src/test/java/org/yaml/snakeyaml/stress/
DParallelTest.java60 int cycles = 200; in run() local
61 for (int i = 0; i < cycles; i++) { in run()
66 float duration = ((time2 - time1) / 1000000) / (float) cycles; in run()
/external/tensorflow/tensorflow/compiler/jit/
Dxla_cluster_util_test.cc51 GraphCycles cycles; in TEST() local
52 TF_ASSERT_OK(CreateCycleDetectionGraph(root.graph(), &cycles).status()); in TEST()
53 EXPECT_FALSE(cycles.ContractEdge(a.node()->id(), b.node()->id())); in TEST()
70 GraphCycles cycles; in TEST() local
71 TF_ASSERT_OK(CreateCycleDetectionGraph(root.graph(), &cycles).status()); in TEST()
72 EXPECT_FALSE(cycles.ContractEdge(a.node()->id(), b.node()->id())); in TEST()
92 GraphCycles cycles; in TEST() local
94 CreateCycleDetectionGraph(root.graph(), &cycles)); in TEST()
/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-mca/X86/
Doption-all-stats-1.s35 # FULLREPORT: Dispatch Logic - number of cycles where we saw N instructions dispatched:
36 # FULLREPORT-NEXT: [# dispatched], [# cycles]
41 # FULLREPORT: Schedulers - number of cycles where we saw N instructions issued:
42 # FULLREPORT-NEXT: [# issued], [# cycles]
/external/mesa3d/src/gallium/drivers/llvmpipe/
Dlp_test_conv.c66 double cycles, in write_tsv_row() argument
71 fprintf(fp, "%.1f\t", cycles / MAX2(src_type.length, dst_type.length)); in write_tsv_row()
164 int64_t cycles[LP_TEST_NUM_SAMPLES]; in test_one() local
258 cycles[i] = end_counter - start_counter; in test_one()
311 sum += cycles[i]; in test_one()
312 sum2 += cycles[i]*cycles[i]; in test_one()
321 if(fabs(cycles[i] - avg) <= 4.0*std) { in test_one()
322 sum += cycles[i]; in test_one()

12345678910>>...19