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/external/mesa3d/src/util/
Ddriconf.h72 #define DRI_CONF_OPT_B(_name, def, _desc) { \ argument
78 .value = { ._bool = def }, \
81 #define DRI_CONF_OPT_I(_name, def, min, max, _desc) { \ argument
88 .value = { ._int = def }, \
91 #define DRI_CONF_OPT_F(_name, def, min, max, _desc) { \ argument
98 .value = { ._float = def }, \
101 #define DRI_CONF_OPT_E(_name, def, min, max, _desc, values) { \ argument
108 .value = { ._int = def }, \
112 #define DRI_CONF_OPT_S(_name, def, _desc) { \ argument
118 .value = { ._string = #def }, \
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMSchedule.td32 // def WriteALUsr : SchedWrite;
33 // def ReadAdvanceALUsr : ScheRead;
36 // def ADDrs : I<>, Sched<[WriteALUsr, ReadAdvanceALUsr, ReadDefault,
45 // def P01 : ProcResource<3>; // ALU unit (3 of it).
48 // def : WriteRes<WriteALUsr, [P01, P01]> {
55 // def : ReadAdvance<ReadAdvanceALUsr, 3>;
61 def WriteALU : SchedWrite;
62 def ReadALU : SchedRead;
65 def WriteALUsi : SchedWrite; // Shift by immediate.
66 def WriteALUsr : SchedWrite; // Shift by register.
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/external/llvm/lib/Target/ARM/
DARMSchedule.td32 // def WriteALUsr : SchedWrite;
33 // def ReadAdvanceALUsr : ScheRead;
36 // def ADDrs : I<>, Sched<[WriteALUsr, ReadAdvanceALUsr, ReadDefault,
45 // def P01 : ProcResource<3>; // ALU unit (3 of it).
48 // def : WriteRes<WriteALUsr, [P01, P01]> {
55 // def : ReadAdvance<ReadAdvanceALUsr, 3>;
58 def WriteALU : SchedWrite;
59 def ReadALU : SchedRead;
62 def WriteALUsi : SchedWrite; // Shift by immediate.
63 def WriteALUsr : SchedWrite; // Shift by register.
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/external/clang/include/clang/Basic/
DStmtNodes.td12 def NullStmt : Stmt;
13 def CompoundStmt : Stmt;
14 def LabelStmt : Stmt;
15 def AttributedStmt : Stmt;
16 def IfStmt : Stmt;
17 def SwitchStmt : Stmt;
18 def WhileStmt : Stmt;
19 def DoStmt : Stmt;
20 def ForStmt : Stmt;
21 def GotoStmt : Stmt;
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DDeclNodes.td13 def TranslationUnit : Decl, DeclContext;
14 def PragmaComment : Decl;
15 def PragmaDetectMismatch : Decl;
16 def ExternCContext : Decl, DeclContext;
17 def Named : Decl<1>;
18 def Namespace : DDecl<Named>, DeclContext;
19 def UsingDirective : DDecl<Named>;
20 def NamespaceAlias : DDecl<Named>;
21 def Label : DDecl<Named>;
22 def Type : DDecl<Named, 1>;
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DDiagnosticGroups.td10 def ImplicitFunctionDeclare : DiagGroup<"implicit-function-declaration">;
11 def ImplicitInt : DiagGroup<"implicit-int">;
14 def Implicit : DiagGroup<"implicit", [
20 def : DiagGroup<"abi">;
21 def AbsoluteValue : DiagGroup<"absolute-value">;
22 def AddressOfTemporary : DiagGroup<"address-of-temporary">;
23 def : DiagGroup<"aggregate-return">;
24 def GNUAlignofExpression : DiagGroup<"gnu-alignof-expression">;
25 def AmbigMemberTemplate : DiagGroup<"ambiguous-member-template">;
26 def GNUAnonymousStruct : DiagGroup<"gnu-anonymous-struct">;
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/external/llvm/lib/Target/X86/
DX86Schedule.td17 def ReadAfterLd : SchedRead;
21 def WriteRMW : SchedWrite;
35 def Ld : SchedWrite;
37 def NAME : X86FoldableSchedWrite {
45 def WriteIMulH : SchedWrite; // Integer multiplication, high part.
47 def WriteLEA : SchedWrite; // LEA instructions can't fold loads.
53 def WriteLoad : SchedWrite;
54 def WriteStore : SchedWrite;
55 def WriteMove : SchedWrite;
59 def WriteZero : SchedWrite;
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/external/llvm/lib/Target/PowerPC/
DPPCSchedule.td13 def IIC_IntSimple : InstrItinClass;
14 def IIC_IntGeneral : InstrItinClass;
15 def IIC_IntCompare : InstrItinClass;
16 def IIC_IntISEL : InstrItinClass;
17 def IIC_IntDivD : InstrItinClass;
18 def IIC_IntDivW : InstrItinClass;
19 def IIC_IntMFFS : InstrItinClass;
20 def IIC_IntMFVSCR : InstrItinClass;
21 def IIC_IntMTFSB0 : InstrItinClass;
22 def IIC_IntMTSRD : InstrItinClass;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCSchedule.td13 def IIC_IntSimple : InstrItinClass;
14 def IIC_IntGeneral : InstrItinClass;
15 def IIC_IntCompare : InstrItinClass;
16 def IIC_IntISEL : InstrItinClass;
17 def IIC_IntDivD : InstrItinClass;
18 def IIC_IntDivW : InstrItinClass;
19 def IIC_IntMFFS : InstrItinClass;
20 def IIC_IntMFVSCR : InstrItinClass;
21 def IIC_IntMTFSB0 : InstrItinClass;
22 def IIC_IntMTSRD : InstrItinClass;
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/external/clang/include/clang/AST/
DCommentHTMLNamedCharacterReferences.td15 def : NCR<"copy", 0x000A9>;
16 def : NCR<"COPY", 0x000A9>;
17 def : NCR<"trade", 0x02122>;
18 def : NCR<"TRADE", 0x02122>;
19 def : NCR<"reg", 0x000AE>;
20 def : NCR<"REG", 0x000AE>;
21 def : NCR<"lt", 0x0003C>;
22 def : NCR<"Lt", 0x0003C>;
23 def : NCR<"LT", 0x0003C>;
24 def : NCR<"gt", 0x0003E>;
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dspill-fold.mir19def dead $x0, 12, implicit-def dead $x1, 12, implicit-def dead $x2, 12, implicit-def dead $x3, 12,…
33def dead $x0, 12, implicit-def dead $x1, 12, implicit-def dead $x2, 12, implicit-def dead $x3, 12,…
47def dead $d0, 12, implicit-def dead $d1, 12, implicit-def dead $d2, 12, implicit-def dead $d3, 12,…
61def dead $x0, 12, implicit-def dead $x1, 12, implicit-def dead $x2, 12, implicit-def dead $x3, 12,…
77def dead $x0, 12, implicit-def dead $x1, 12, implicit-def dead $x2, 12, implicit-def dead $x3, 12,…
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsScheduleGeneric.td17 def MipsGenericModel : SchedMachineModel {
40 def GenericALU : ProcResource<1> { let BufferSize = 1; }
41 def GenericIssueALU : ProcResource<1> { let Super = GenericALU; }
43 def GenericWriteALU : SchedWriteRes<[GenericIssueALU]>;
48 def : ItinRW<[GenericWriteALU], [II_ADD, II_ADDU, II_ADDI, II_ADDIU, II_ANDI,
57 def : InstRW<[GenericWriteALU], (instrs COPY)>;
59 def GenericMDU : ProcResource<1> { let BufferSize = 1; }
60 def GenericIssueMDU : ProcResource<1> { let Super = GenericALU; }
61 def GenericIssueDIV : ProcResource<1> { let Super = GenericMDU; }
62 def GenericWriteHILO : SchedWriteRes<[GenericIssueMDU]>;
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DMipsSchedule.td13 def ALU : FuncUnit;
14 def IMULDIV : FuncUnit;
20 def IIM16Alu : InstrItinClass;
21 def IIPseudo : InstrItinClass;
23 def II_ABS : InstrItinClass;
24 def II_ADDI : InstrItinClass;
25 def II_ADDIU : InstrItinClass;
26 def II_ADDIUPC : InstrItinClass;
27 def II_ADD : InstrItinClass;
28 def II_ADDU : InstrItinClass;
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/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsics.td227 def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>;
228 def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>;
229 def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>;
230 def : T_RR_pat <M2_mpy_lh_s0, int_hexagon_M2_mpy_lh_s0>;
231 def : T_RR_pat <M2_mpy_hl_s1, int_hexagon_M2_mpy_hl_s1>;
232 def : T_RR_pat <M2_mpy_hl_s0, int_hexagon_M2_mpy_hl_s0>;
233 def : T_RR_pat <M2_mpy_hh_s1, int_hexagon_M2_mpy_hh_s1>;
234 def : T_RR_pat <M2_mpy_hh_s0, int_hexagon_M2_mpy_hh_s0>;
236 def : T_RR_pat <M2_mpyu_ll_s1, int_hexagon_M2_mpyu_ll_s1>;
237 def : T_RR_pat <M2_mpyu_ll_s0, int_hexagon_M2_mpyu_ll_s0>;
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DHexagonIntrinsicsV4.td17 def : T_PP_pat <M4_vrmpyeh_s0, int_hexagon_M4_vrmpyeh_s0>;
18 def : T_PP_pat <M4_vrmpyeh_s1, int_hexagon_M4_vrmpyeh_s1>;
21 def : T_PP_pat <M4_vrmpyoh_s0, int_hexagon_M4_vrmpyoh_s0>;
22 def : T_PP_pat <M4_vrmpyoh_s1, int_hexagon_M4_vrmpyoh_s1>;
25 def : T_PPP_pat <M4_vrmpyeh_acc_s0, int_hexagon_M4_vrmpyeh_acc_s0>;
26 def : T_PPP_pat <M4_vrmpyeh_acc_s1, int_hexagon_M4_vrmpyeh_acc_s1>;
29 def : T_PPP_pat <M4_vrmpyoh_acc_s0, int_hexagon_M4_vrmpyoh_acc_s0>;
30 def : T_PPP_pat <M4_vrmpyoh_acc_s1, int_hexagon_M4_vrmpyoh_acc_s1>;
34 def : T_RR_pat <M2_vmpy2su_s0, int_hexagon_M2_vmpy2su_s0>;
35 def : T_RR_pat <M2_vmpy2su_s1, int_hexagon_M2_vmpy2su_s1>;
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DHexagonIntrinsicsV5.td13 def : T_PP_pat <M5_vrmpybsu, int_hexagon_M5_vrmpybsu>;
14 def : T_PP_pat <M5_vrmpybuu, int_hexagon_M5_vrmpybuu>;
16 def : T_PP_pat <M5_vdmpybsu, int_hexagon_M5_vdmpybsu>;
18 def : T_PPP_pat <M5_vrmacbsu, int_hexagon_M5_vrmacbsu>;
19 def : T_PPP_pat <M5_vrmacbuu, int_hexagon_M5_vrmacbuu>;
21 def : T_PPP_pat <M5_vdmacbsu, int_hexagon_M5_vdmacbsu>;
25 def : T_RR_pat <M5_vmpybsu, int_hexagon_M5_vmpybsu>;
26 def : T_RR_pat <M5_vmpybuu, int_hexagon_M5_vmpybuu>;
29 def : T_PRR_pat <M5_vmacbsu, int_hexagon_M5_vmacbsu>;
30 def : T_PRR_pat <M5_vmacbuu, int_hexagon_M5_vmacbuu>;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV4.td17 def : T_PP_pat <M4_vrmpyeh_s0, int_hexagon_M4_vrmpyeh_s0>;
18 def : T_PP_pat <M4_vrmpyeh_s1, int_hexagon_M4_vrmpyeh_s1>;
21 def : T_PP_pat <M4_vrmpyoh_s0, int_hexagon_M4_vrmpyoh_s0>;
22 def : T_PP_pat <M4_vrmpyoh_s1, int_hexagon_M4_vrmpyoh_s1>;
25 def : T_PPP_pat <M4_vrmpyeh_acc_s0, int_hexagon_M4_vrmpyeh_acc_s0>;
26 def : T_PPP_pat <M4_vrmpyeh_acc_s1, int_hexagon_M4_vrmpyeh_acc_s1>;
29 def : T_PPP_pat <M4_vrmpyoh_acc_s0, int_hexagon_M4_vrmpyoh_acc_s0>;
30 def : T_PPP_pat <M4_vrmpyoh_acc_s1, int_hexagon_M4_vrmpyoh_acc_s1>;
34 def : T_RR_pat <M2_vmpy2su_s0, int_hexagon_M2_vmpy2su_s0>;
35 def : T_RR_pat <M2_vmpy2su_s1, int_hexagon_M2_vmpy2su_s1>;
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DHexagonIntrinsics.td227 def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>;
228 def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>;
229 def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>;
230 def : T_RR_pat <M2_mpy_lh_s0, int_hexagon_M2_mpy_lh_s0>;
231 def : T_RR_pat <M2_mpy_hl_s1, int_hexagon_M2_mpy_hl_s1>;
232 def : T_RR_pat <M2_mpy_hl_s0, int_hexagon_M2_mpy_hl_s0>;
233 def : T_RR_pat <M2_mpy_hh_s1, int_hexagon_M2_mpy_hh_s1>;
234 def : T_RR_pat <M2_mpy_hh_s0, int_hexagon_M2_mpy_hh_s0>;
236 def : T_RR_pat <M2_mpyu_ll_s1, int_hexagon_M2_mpyu_ll_s1>;
237 def : T_RR_pat <M2_mpyu_ll_s0, int_hexagon_M2_mpyu_ll_s0>;
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DHexagonIntrinsicsV5.td13 def : T_PP_pat <M5_vrmpybsu, int_hexagon_M5_vrmpybsu>;
14 def : T_PP_pat <M5_vrmpybuu, int_hexagon_M5_vrmpybuu>;
16 def : T_PP_pat <M5_vdmpybsu, int_hexagon_M5_vdmpybsu>;
18 def : T_PPP_pat <M5_vrmacbsu, int_hexagon_M5_vrmacbsu>;
19 def : T_PPP_pat <M5_vrmacbuu, int_hexagon_M5_vrmacbuu>;
21 def : T_PPP_pat <M5_vdmacbsu, int_hexagon_M5_vdmacbsu>;
25 def : T_RR_pat <M5_vmpybsu, int_hexagon_M5_vmpybsu>;
26 def : T_RR_pat <M5_vmpybuu, int_hexagon_M5_vmpybuu>;
29 def : T_PRR_pat <M5_vmacbsu, int_hexagon_M5_vmacbsu>;
30 def : T_PRR_pat <M5_vmacbuu, int_hexagon_M5_vmacbuu>;
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/external/llvm/lib/Target/AVR/
DAVR.td53 def FeatureSRAM : SubtargetFeature<"sram", "m_hasSRAM", "true",
57 def FeatureJMPCALL : SubtargetFeature<"jmpcall", "m_hasJMPCALL", "true",
63 def FeatureIJMPCALL : SubtargetFeature<"ijmpcall", "m_hasIJMPCALL",
69 def FeatureEIJMPCALL : SubtargetFeature<"eijmpcall", "m_hasEIJMPCALL",
74 def FeatureADDSUBIW : SubtargetFeature<"addsubiw", "m_hasADDSUBIW",
79 def FeatureSmallStack : SubtargetFeature<"smallstack", "m_hasSmallStack",
84 def FeatureMOVW : SubtargetFeature<"movw", "m_hasMOVW", "true",
89 def FeatureLPM : SubtargetFeature<"lpm", "m_hasLPM", "true",
93 def FeatureLPMX : SubtargetFeature<"lpmx", "m_hasLPMX", "true",
98 def FeatureELPM : SubtargetFeature<"elpm", "m_hasELPM", "true",
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRDevices.td35 def FeatureSRAM : SubtargetFeature<"sram", "m_hasSRAM", "true",
39 def FeatureJMPCALL : SubtargetFeature<"jmpcall", "m_hasJMPCALL", "true",
45 def FeatureIJMPCALL : SubtargetFeature<"ijmpcall", "m_hasIJMPCALL",
51 def FeatureEIJMPCALL : SubtargetFeature<"eijmpcall", "m_hasEIJMPCALL",
56 def FeatureADDSUBIW : SubtargetFeature<"addsubiw", "m_hasADDSUBIW",
61 def FeatureSmallStack : SubtargetFeature<"smallstack", "m_hasSmallStack",
66 def FeatureMOVW : SubtargetFeature<"movw", "m_hasMOVW", "true",
71 def FeatureLPM : SubtargetFeature<"lpm", "m_hasLPM", "true",
75 def FeatureLPMX : SubtargetFeature<"lpmx", "m_hasLPMX", "true",
80 def FeatureELPM : SubtargetFeature<"elpm", "m_hasELPM", "true",
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td25 def sub_even : SubRegIndex<32>;
26 def sub_odd : SubRegIndex<32, 32>;
27 def sub_even64 : SubRegIndex<64>;
28 def sub_odd64 : SubRegIndex<64, 64>;
59 def ICC : SparcCtrlReg<0, "ICC">; // This represents icc and xcc in 64-bit code.
61 def FCC#I : SparcCtrlReg<I, "FCC"#I>;
63 def FSR : SparcCtrlReg<0, "FSR">; // Floating-point state register.
65 def FQ : SparcCtrlReg<0, "FQ">; // Floating-point deferred-trap queue.
67 def CPSR : SparcCtrlReg<0, "CPSR">; // Co-processor state register.
69 def CPQ : SparcCtrlReg<0, "CPQ">; // Co-processor queue.
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/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td25 def sub_even : SubRegIndex<32>;
26 def sub_odd : SubRegIndex<32, 32>;
27 def sub_even64 : SubRegIndex<64>;
28 def sub_odd64 : SubRegIndex<64, 64>;
59 def ICC : SparcCtrlReg<0, "ICC">; // This represents icc and xcc in 64-bit code.
61 def FCC#I : SparcCtrlReg<I, "FCC"#I>;
63 def FSR : SparcCtrlReg<0, "FSR">; // Floating-point state register.
65 def FQ : SparcCtrlReg<0, "FQ">; // Floating-point deferred-trap queue.
67 def CPSR : SparcCtrlReg<0, "CPSR">; // Co-processor state register.
69 def CPQ : SparcCtrlReg<0, "CPQ">; // Co-processor queue.
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/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
DNestedForeach.td14 def S#R#M#P : Droid<S, R, M, P>;
22 def Z#i#_#j;
24 // CHECK: def C2D0
25 // CHECK: def C2D2
26 // CHECK: def C2D4
27 // CHECK: def C2P0
28 // CHECK: def C2P2
29 // CHECK: def C2P4
30 // CHECK: def C2Q0
31 // CHECK: def C2Q2
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/external/llvm/lib/Target/Mips/
DMipsSchedule.td13 def ALU : FuncUnit;
14 def IMULDIV : FuncUnit;
20 def IIM16Alu : InstrItinClass;
21 def IIPseudo : InstrItinClass;
23 def II_ABS : InstrItinClass;
24 def II_ADDI : InstrItinClass;
25 def II_ADDIU : InstrItinClass;
26 def II_ADDIUPC : InstrItinClass;
27 def II_ADD : InstrItinClass;
28 def II_ADDU : InstrItinClass;
[all …]

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