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Searched refs:desc_mem (Results 1 – 9 of 9) sorted by relevance

/external/u-boot/drivers/dma/
Dkeystone_nav.c21 .desc_mem = (void *)CONFIG_KSNAV_QM_DESC_SETUP_BASE,
61 qm_cfg->desc_mem[0].base_addr = (u32)desc_pool; in _qm_init()
62 qm_cfg->desc_mem[0].start_idx = 0; in _qm_init()
63 qm_cfg->desc_mem[0].desc_reg_size = in _qm_init()
92 qm_cfg->desc_mem[j].base_addr = 0; in qm_close()
93 qm_cfg->desc_mem[j].start_idx = 0; in qm_close()
94 qm_cfg->desc_mem[j].desc_reg_size = 0; in qm_close()
/external/u-boot/drivers/net/
Daltera_tse.c583 void *base, *desc_mem = NULL; in altera_tse_probe() local
627 desc_mem = base; in altera_tse_probe()
645 if (!desc_mem) { in altera_tse_probe()
646 desc_mem = dma_alloc_coherent(len, &addr); in altera_tse_probe()
647 if (!desc_mem) in altera_tse_probe()
650 memset(desc_mem, 0, len); in altera_tse_probe()
651 priv->tx_desc = desc_mem; in altera_tse_probe()
/external/mesa3d/src/intel/vulkan/
Danv_descriptor_set.c1080 set->desc_mem.offset = pool_vma_offset - POOL_HEAP_OFFSET; in anv_descriptor_set_create()
1081 set->desc_mem.alloc_size = set_buffer_size; in anv_descriptor_set_create()
1082 set->desc_mem.map = pool->bo->map + set->desc_mem.offset; in anv_descriptor_set_create()
1093 .offset = set->desc_mem.offset, in anv_descriptor_set_create()
1097 set->desc_mem = ANV_STATE_NULL; in anv_descriptor_set_create()
1164 if (set->desc_mem.alloc_size) { in anv_descriptor_set_destroy()
1166 (uint64_t)set->desc_mem.offset + POOL_HEAP_OFFSET, in anv_descriptor_set_destroy()
1167 set->desc_mem.alloc_size); in anv_descriptor_set_destroy()
1324 void *desc_map = set->desc_mem.map + bind_layout->descriptor_offset + in anv_descriptor_set_write_image_view()
1415 void *desc_map = set->desc_mem.map + bind_layout->descriptor_offset + in anv_descriptor_set_write_buffer_view()
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Danv_cmd_buffer.c1242 set->desc_mem.alloc_size < layout->descriptor_buffer_size)) { in anv_cmd_buffer_push_descriptor_set()
1246 struct anv_state desc_mem = in anv_cmd_buffer_push_descriptor_set() local
1249 if (set->desc_mem.alloc_size) { in anv_cmd_buffer_push_descriptor_set()
1251 memcpy(desc_mem.map, set->desc_mem.map, in anv_cmd_buffer_push_descriptor_set()
1252 MIN2(desc_mem.alloc_size, set->desc_mem.alloc_size)); in anv_cmd_buffer_push_descriptor_set()
1254 set->desc_mem = desc_mem; in anv_cmd_buffer_push_descriptor_set()
1258 .offset = set->desc_mem.offset, in anv_cmd_buffer_push_descriptor_set()
DgenX_cmd_buffer.c2521 .offset = set->desc_mem.offset, in anv_descriptor_set_address()
2533 .offset = set->desc_mem.offset, in anv_descriptor_set_address()
2660 assert(set->desc_mem.alloc_size); in emit_binding_table()
3080 assert(range->start * 32 < set->desc_mem.alloc_size); in get_push_range_bound_size()
3081 assert((range->start + range->length) * 32 <= set->desc_mem.alloc_size); in get_push_range_bound_size()
3082 return set->desc_mem.alloc_size; in get_push_range_bound_size()
Danv_private.h2084 struct anv_state desc_mem; member
/external/crosvm/devices/src/virtio/
Dwl.rs296 desc_mem: VolatileSlice, in encode_vfd_new()
318 desc_mem.get_ref(0)?.store(ctrl_vfd_new); in encode_vfd_new()
324 desc_mem: VolatileSlice, in encode_vfd_new_dmabuf()
351 desc_mem.get_ref(0)?.store(ctrl_vfd_new_dmabuf); in encode_vfd_new_dmabuf()
356 desc_mem: VolatileSlice, in encode_vfd_recv()
369 desc_mem.get_ref(0)?.store(ctrl_vfd_recv); in encode_vfd_recv()
371 let vfd_slice = desc_mem.get_slice( in encode_vfd_recv()
381 let data_slice = desc_mem.get_slice( in encode_vfd_recv()
390 fn encode_vfd_hup(desc_mem: VolatileSlice, vfd_id: u32) -> WlResult<u32> { in encode_vfd_hup()
399 desc_mem.get_ref(0)?.store(ctrl_vfd_new); in encode_vfd_hup()
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/external/u-boot/arch/arm/include/asm/ti-common/
Dkeystone_nav.h65 struct descr_mem_setup_reg *desc_mem; member
/external/crosvm/devices/src/virtio/gpu/
Dmod.rs366 if let Ok(desc_mem) = mem.get_slice(desc.addr.offset(), desc.len as u64) { in process_descriptor()
367 match GpuCommand::decode(desc_mem) { in process_descriptor()