| /external/elfutils/lib/ |
| D | next_prime.c | 38 size_t divn = 3; in is_prime() local
39 size_t sq = divn * divn; in is_prime()
41 while (sq < candidate && candidate % divn != 0) in is_prime()
44 ++divn; in is_prime()
45 sq += 4 * divn; in is_prime()
48 ++divn; in is_prime()
51 return candidate % divn != 0; in is_prime()
|
| /external/u-boot/arch/arm/mach-uniphier/clk/ |
| D | pll-base-ld20.c | 33 unsigned int ssc_rate, unsigned int divn) in uniphier_ld20_sscpll_init() argument
43 divn * 512)); in uniphier_ld20_sscpll_init()
50 divn * 512)); in uniphier_ld20_sscpll_init()
|
| D | pll.h | 15 unsigned int ssc_rate, unsigned int divn);
|
| /external/u-boot/arch/arm/include/asm/arch-tegra/ |
| D | clock.h | 61 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
88 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
|
| D | warmboot.h | 73 u32 divn:10; member
|
| /external/u-boot/arch/arm/mach-tegra/tegra20/ |
| D | warmboot.c | 153 u32 divm, divn, divp, cpcon, lfcon; in warmboot_save_sdram_params() local
155 if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp, in warmboot_save_sdram_params()
159 scratch2.pllm_base_divn = divn; in warmboot_save_sdram_params()
|
| D | warmboot_avp.c | 168 pllx_base.divn = scratch3.pllx_base_divn; in wb_start()
|
| /external/u-boot/arch/arm/mach-tegra/ |
| D | cpu.c | 170 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, in pllx_set_rate() argument
188 reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift); in pllx_set_rate()
202 if (divn > 600) in pllx_set_rate()
|
| D | clock.c | 90 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, in clock_ll_read_pll() argument
104 *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask; in clock_ll_read_pll()
114 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, in clock_start_pll() argument
148 data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift); in clock_start_pll()
|
| /external/u-boot/arch/arm/mach-tegra/tegra124/ |
| D | clock.c | 1066 u32 divm, divn, divp, cpcon; in clock_set_display_rate() local
1093 divn = vco / cf; in clock_set_display_rate()
1094 if (divn >= max_n) in clock_set_display_rate()
1097 diff = vco - divn * cf; in clock_set_display_rate()
1098 if (divn + 1 < max_n && diff > cf / 2) { in clock_set_display_rate()
1099 divn++; in clock_set_display_rate()
1108 best_n = divn; in clock_set_display_rate()
|
| /external/u-boot/drivers/clk/ |
| D | clk_stm32mp1.c | 881 int divm, divn; in pll_get_fvco() local
889 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; in pll_get_fvco()
902 (((divn + 1) << 13) + fracv), in pll_get_fvco()
905 fvco = (ulong)(refclk * (divn + 1) / (divm + 1)); in pll_get_fvco()
1470 int divm, divn, divy; in pll_set_rate() local
1506 divn = (value >> 13) - 1; in pll_set_rate()
1507 if (divn < DIVN_MIN || in pll_set_rate()
1508 divn > stm32mp1_pll[type].divn_max) { in pll_set_rate()
1509 pr_err("divn invalid = %d", divn); in pll_set_rate()
1512 fracv = value - ((divn + 1) << 13); in pll_set_rate()
[all …]
|
| D | clk_stm32h7.c | 321 u16 divn; member
334 .divn = 80,
400 pll1divr |= (sys_pll_psc.divn - 1); in configure_clocks()
|
| /external/arm-trusted-firmware/drivers/st/clk/ |
| D | stm32mp1_clk.c | 676 uint32_t cfgr1, fracr, divm, divn; in stm32mp1_pll_get_fvco() local
683 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; in stm32mp1_pll_get_fvco()
698 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; in stm32mp1_pll_get_fvco()
703 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); in stm32mp1_pll_get_fvco()
|