| /external/u-boot/drivers/ram/rockchip/ |
| D | sdram_px30.c | 211 if (sdram_params->base.dramtype == DDR4) { in calculate_ddrconfig()
244 if (sdram_params->base.dramtype == DDR4) in set_ctl_address_map()
261 if (sdram_params->base.dramtype == DDR4) { in set_ctl_address_map()
283 if ((sdram_params->base.dramtype == LPDDR3 || in set_ctl_address_map()
284 sdram_params->base.dramtype == LPDDR2) && in set_ctl_address_map()
287 if (sdram_params->base.dramtype == DDR4 && cap_info->bw != 0x2) in set_ctl_address_map()
341 static int data_training(struct dram_info *dram, u32 cs, u32 dramtype) in data_training() argument
354 ret = phy_data_training(dram->phy, cs, dramtype); in data_training()
382 cs_cap[0] = sdram_get_cs_cap(cap_info, 0, base->dramtype); in sdram_msch_config()
383 cs_cap[1] = sdram_get_cs_cap(cap_info, 1, base->dramtype); in sdram_msch_config()
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| D | sdram_pctl_px30.c | 33 u32 dramtype) in pctl_write_mr() argument
37 if (dramtype == DDR3 || dramtype == DDR4) { in pctl_write_mr()
62 u32 dramtype) in pctl_write_vrefdq() argument
67 if (dramtype != DDR4 || vrefrate < 4500 || in pctl_write_vrefdq()
85 pctl_write_mr(pctl_base, rank, 6, value | (1 << 7), dramtype); in pctl_write_vrefdq()
88 pctl_write_mr(pctl_base, rank, 6, value | (1 << 7), dramtype); in pctl_write_vrefdq()
90 pctl_write_mr(pctl_base, rank, 6, value | (0 << 7), dramtype); in pctl_write_vrefdq()
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| D | sdram_rk3328.c | 150 if (sdram_params->base.dramtype == DDR4) { in calculate_ddrconfig()
223 if (sdram_params->base.dramtype == LPDDR3 && cap_info->row_3_4) in set_ctl_address_map()
225 if (sdram_params->base.dramtype == DDR4 && cap_info->bw == 0x1) in set_ctl_address_map()
232 static int data_training(struct dram_info *dram, u32 cs, u32 dramtype) in data_training() argument
245 ret = phy_data_training(dram->phy, cs, dramtype); in data_training()
376 if (data_training(dram, 0, sdram_params->base.dramtype) != 0) { in sdram_init()
380 if (data_training(dram, 1, sdram_params->base.dramtype) != 0) { in sdram_init()
385 if (sdram_params->base.dramtype == DDR4) in sdram_init()
387 sdram_params->base.dramtype); in sdram_init()
417 u32 dram_type = sdram_params->base.dramtype; in dram_detect_cap()
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| D | sdram_rk3399.c | 325 if (params->base.dramtype == LPDDR4) { in set_memory_map()
336 if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3) in set_memory_map()
352 if (params->base.dramtype == LPDDR4) { in phy_io_config()
372 } else if (params->base.dramtype == LPDDR3) { in phy_io_config()
433 } else if (params->base.dramtype == DDR3) { in phy_io_config()
478 if (params->base.dramtype == LPDDR4) { in phy_io_config()
538 if (params->base.dramtype == LPDDR4) { in phy_io_config()
578 if (params->base.dramtype == LPDDR4) { in set_ds_odt()
625 } else if (params->base.dramtype == LPDDR3) { in set_ds_odt()
660 if (params->base.dramtype == LPDDR4) in set_ds_odt()
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| D | sdram_rk3288.c | 172 static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype) in dfi_cfg() argument
249 switch (sdram_params->base.dramtype) { in pctl_cfg()
318 switch (sdram_params->base.dramtype) { in phy_cfg()
385 u32 dramtype) in memory_init() argument
390 | (dramtype == DDR3 ? PIR_DRAMRST : 0))); in memory_init()
487 if (sdram_params->base.dramtype != LPDDR3) in data_training()
527 if (sdram_params->base.dramtype != LPDDR3) in data_training()
596 sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; in dram_all_config()
658 if (sdram_params->base.dramtype == LPDDR3) { in sdram_rank_bw_detect()
789 if ((sdram_params->base.dramtype == DDR3 && in sdram_init()
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| D | sdram_rk322x.c | 165 u32 dramtype = sdram_params->base.dramtype; in memory_init() local
167 if (dramtype == DDR3) { in memory_init()
221 if (dramtype == LPDDR3) in memory_init()
405 u32 dramtype = sdram_params->base.dramtype; in pctl_cfg() local
424 if (dramtype == DDR3) { in pctl_cfg()
445 if (dramtype == LPDDR2) { in pctl_cfg()
483 switch (sdram_params->base.dramtype) { in phy_cfg()
501 if (sdram_params->base.dramtype == LPDDR2) in phy_cfg()
582 sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; in dram_all_config()
606 if (sdram_params->base.dramtype == DDR3) in dram_cap_detect()
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| D | sdram_common.c | 14 void sdram_print_dram_type(unsigned char dramtype) in sdram_print_dram_type() argument
16 switch (dramtype) { in sdram_print_dram_type()
46 sdram_print_dram_type(base->dramtype); in sdram_print_ddr_info()
58 if (base->dramtype == DDR4) { in sdram_print_ddr_info()
83 cap = sdram_get_cs_cap(cap_info, 3, base->dramtype); in sdram_print_ddr_info()
173 *p_os_reg2 |= SYS_REG_ENC_DDRTYPE(base->dramtype); in sdram_org_config()
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| D | sdram_phy_px30.c | 116 int phy_data_training(void __iomem *phy_base, u32 cs, u32 dramtype) in phy_data_training() argument
130 if (dramtype == DDR4) { in phy_data_training()
148 if (dramtype == DDR4) { in phy_data_training()
195 sdram_phy_set_ds_odt(phy_base, base->dramtype); in phy_cfg()
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| D | sdram_rk3188.c | 172 static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype) in dfi_cfg() argument
232 switch (sdram_params->base.dramtype) { in pctl_cfg()
280 switch (sdram_params->base.dramtype) { in phy_cfg()
326 u32 dramtype) in memory_init() argument
331 | (dramtype == DDR3 ? PIR_DRAMRST : 0))); in memory_init()
428 if (sdram_params->base.dramtype != LPDDR3) in data_training()
468 if (sdram_params->base.dramtype != LPDDR3) in data_training()
538 sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; in dram_all_config()
604 if (sdram_params->base.dramtype == LPDDR3) { in sdram_rank_bw_detect()
716 if ((sdram_params->base.dramtype == DDR3 && in sdram_init()
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| D | sdram-px30-ddr3-detect-333.inc | 28 .dramtype = DDR3,
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| D | sdram-px30-lpddr3-detect-333.inc | 28 .dramtype = LPDDR3,
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| D | sdram-px30-ddr4-detect-333.inc | 28 .dramtype = DDR4,
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| D | sdram-px30-lpddr2-detect-333.inc | 28 .dramtype = LPDDR2,
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| D | sdram-rk3399-lpddr4-400.inc | 78 .dramtype = LPDDR4,
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| D | sdram-rk3399-lpddr4-800.inc | 78 .dramtype = LPDDR4,
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| /external/u-boot/arch/arm/include/asm/arch-rockchip/ |
| D | sdram_common.h | 42 unsigned int dramtype; member
118 inline void sdram_print_dram_type(unsigned char dramtype) in sdram_print_dram_type() argument
131 void sdram_print_dram_type(unsigned char dramtype);
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| D | sdram_pctl_px30.h | 126 u32 dramtype);
128 u32 dramtype);
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| D | sdram_phy_px30.h | 60 int phy_data_training(void __iomem *phy_base, u32 cs, u32 dramtype);
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| D | sdram_rk3288.h | 87 u32 dramtype; member
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| D | sdram_rk322x.h | 263 u32 dramtype; member
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| /external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/ |
| D | suspend.c | 192 if (sdram_params->dramtype == LPDDR4) in data_training()
201 if (sdram_params->dramtype == LPDDR4) { in data_training()
206 } else if (sdram_params->dramtype == LPDDR3) { in data_training()
209 } else if (sdram_params->dramtype == DDR3) { in data_training()
788 if (sdram_params->dramtype == LPDDR3) in dmc_resume()
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| D | dram.h | 142 unsigned char dramtype; member
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| D | dram.c | 20 sdram_config.dramtype = SYS_REG_DEC_DDRTYPE(os_reg2_val); in dram_init()
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| D | dfs.c | 194 ptiming_config->dram_type = sdram_params->dramtype; in sdram_timing_cfg_init()
196 switch (sdram_params->dramtype) { in sdram_timing_cfg_init()
1840 get_dram_drv_odt_val(sdram_config.dramtype, in dram_dfs_init()
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| /external/u-boot/arch/arm/include/asm/arch-spear/ |
| D | spr_defs.h | 32 int dramtype; member
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