Searched refs:dv_ddr2_regs_ctrl (Results 1 – 2 of 2) sorted by relevance
187 writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr); in da850_ddr_setup()206 setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK); in da850_ddr_setup()216 writel(tmp, &dv_ddr2_regs_ctrl->sdbcr); in da850_ddr_setup()222 &dv_ddr2_regs_ctrl->sdbcr2); in da850_ddr_setup()224 writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); in da850_ddr_setup()225 writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); in da850_ddr_setup()229 writel(tmp, &dv_ddr2_regs_ctrl->sdbcr); in da850_ddr_setup()238 &dv_ddr2_regs_ctrl->sdrcr); in da850_ddr_setup()246 clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, in da850_ddr_setup()248 writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr); in da850_ddr_setup()
13 struct dv_ddr2_regs_ctrl { struct80 #define dv_ddr2_regs_ctrl \ macro81 ((struct dv_ddr2_regs_ctrl *)DAVINCI_DDR_EMIF_CTRL_BASE)