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Searched refs:extr (Results 1 – 25 of 84) sorted by relevance

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/external/llvm/test/MC/AArch64/
Darm64-bitfield-encoding.s34 extr w1, w2, w3, #15
35 extr x2, x3, x4, #1
37 ; CHECK: extr w1, w2, w3, #15 ; encoding: [0x41,0x3c,0x83,0x13]
38 ; CHECK: extr x2, x3, x4, #1 ; encoding: [0x62,0x04,0xc4,0x93]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Darm64-bitfield-encoding.s34 extr w1, w2, w3, #15
35 extr x2, x3, x4, #1
37 ; CHECK: extr w1, w2, w3, #15 ; encoding: [0x41,0x3c,0x83,0x13]
38 ; CHECK: extr x2, x3, x4, #1 ; encoding: [0x62,0x04,0xc4,0x93]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dknownbits-intrinsics-binop.ll17 %extr = extractvalue {<4 x i32>, i32} %call, 0
18 %and = and <4 x i32> %extr, <i32 1, i32 1, i32 1, i32 1>
32 %extr = extractvalue {<4 x i32>, i32} %call, 0
33 %and = and <4 x i32> %extr, <i32 1, i32 1, i32 1, i32 1>
45 %extr = extractvalue {<8 x i16>, i32} %call, 0
46 %and = and <8 x i16> %extr, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
59 %extr = extractvalue {<8 x i16>, i32} %call, 0
60 %and = and <8 x i16> %extr, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
73 %extr = extractvalue {<16 x i8>, i32} %call, 0
74 %and = and <16 x i8> %extr, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1,
[all …]
Dsignbits-intrinsics-binop.ll17 %extr = extractvalue {<4 x i32>, i32} %call, 0
18 %trunc = trunc <4 x i32> %extr to <4 x i16>
31 %extr = extractvalue {<8 x i16>, i32} %call, 0
32 %trunc = trunc <8 x i16> %extr to <8 x i8>
46 %extr = extractvalue {<16 x i8>, i32} %call, 0
47 %trunc = trunc <16 x i8> %extr to <16 x i4>
63 %extr = extractvalue {<4 x i32>, i32} %call, 0
64 %trunc = trunc <4 x i32> %extr to <4 x i16>
77 %extr = extractvalue {<8 x i16>, i32} %call, 0
78 %trunc = trunc <8 x i16> %extr to <8 x i8>
[all …]
Ddag-combine-03.ll16 %extr = extractelement <2 x i1> %xor, i32 0
27 %sel = select i1 %extr, i64 %add, i64 0
/external/u-boot/drivers/spi/
Drenesas_rpc_spi.c159 fdt_addr_t extr; member
165 fdt_addr_t extr; member
355 memcpy_fromio(din, (void *)(priv->extr + offset), rlen); in rpc_spi_xfer()
357 readl(priv->extr); /* Dummy read */ in rpc_spi_xfer()
411 priv->extr = plat->extr; in rpc_spi_probe()
423 plat->extr = dev_read_addr_index(bus, 1); in rpc_spi_ofdata_to_platdata()
/external/llvm/test/CodeGen/AArch64/
Darm64-extract.ll29 ; CHECK: extr {{w[0-9]+}}, w0, w1, #26
41 ; CHECK: extr {{x[0-9]+}}, x0, x1, #40
54 ; CHECK-NOT: extr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, #{{[0-9]+}}
Dextract.ll28 ; CHECK: extr {{w[0-9]+}}, w0, w1, #26
40 ; CHECK: extr {{x[0-9]+}}, x0, x1, #40
53 ; CHECK-NOT: extr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, #{{[0-9]+}}
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dextract.ll28 ; CHECK: extr {{w[0-9]+}}, w0, w1, #26
40 ; CHECK: extr {{x[0-9]+}}, x0, x1, #40
53 ; CHECK-NOT: extr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, #{{[0-9]+}}
Darm64-extract.ll28 ; CHECK: extr {{w[0-9]+}}, w0, w1, #26
40 ; CHECK: extr {{x[0-9]+}}, x0, x1, #40
53 ; CHECK-NOT: extr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, #{{[0-9]+}}
Dfunnel-shift.ll102 ; With constant shift amount, this is 'extr'.
107 ; CHECK-NEXT: extr w0, w0, w1, #23
118 ; CHECK-NEXT: extr w0, w0, w1, #23
129 ; CHECK-NEXT: extr x0, x0, x1, #23
234 ; With constant shift amount, this is 'extr'.
239 ; CHECK-NEXT: extr w0, w0, w1, #9
250 ; CHECK-NEXT: extr w0, w0, w1, #9
261 ; CHECK-NEXT: extr x0, x0, x1, #41
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Darm64-bitfield.txt28 # CHECK: extr w1, w2, w3, #15
29 # CHECK: extr x2, x3, x4, #1
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-bitfield.txt28 # CHECK: extr w1, w2, w3, #15
29 # CHECK: extr x2, x3, x4, #1
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/dsp/
Dinvalid.s8 extr.w $2, $ac1, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
9 extr.w $2, $ac1, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
Dvalid.s37extr.w $7, $ac0, 31 # CHECK: extr.w $7, $ac0, 31 # encoding: [0x7f,0x…
/external/llvm/test/MC/Mips/dsp/
Dinvalid.s8 extr.w $2, $ac1, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
9 extr.w $2, $ac1, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
Dvalid.s37extr.w $7, $ac0, 31 # CHECK: extr.w $7, $ac0, 31 # encoding: [0x7f,0x…
/external/boringssl/linux-aarch64/crypto/fipsmodule/
Darmv8-mont.S594 extr x15,x16,x15,#63
599 extr x16,x17,x16,#63
608 extr x17,x14,x17,#63
611 extr x14,x15,x14,#63
615 extr x15,x16,x15,#63
617 extr x16,x17,x16,#63
626 extr x17,x14,x17,#63
630 extr x14,x15,x14,#63
633 extr x15,x16,x15,#63
638 extr x16,x17,x16,#63
[all …]
/external/boringssl/ios-aarch64/crypto/fipsmodule/
Darmv8-mont.S593 extr x15,x16,x15,#63
598 extr x16,x17,x16,#63
607 extr x17,x14,x17,#63
610 extr x14,x15,x14,#63
614 extr x15,x16,x15,#63
616 extr x16,x17,x16,#63
625 extr x17,x14,x17,#63
629 extr x14,x15,x14,#63
632 extr x15,x16,x15,#63
637 extr x16,x17,x16,#63
[all …]
/external/mesa3d/src/freedreno/rnn/
Dutil.h86 #define extr(a, b, c) ((uint64_t)(a) << (64 - (b) - (c)) >> (64 - (c))) macro
/external/llvm/test/CodeGen/Mips/
Ddsp-r1.ll6 ; CHECK: extr.w
8 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 15)
12 declare i32 @llvm.mips.extr.w(i64, i32) nounwind
18 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 %a1)
26 %1 = tail call i32 @llvm.mips.extr.r.w(i64 %a0, i32 15)
30 declare i32 @llvm.mips.extr.r.w(i64, i32) nounwind
36 %1 = tail call i32 @llvm.mips.extr.s.h(i64 %a0, i32 %a1)
40 declare i32 @llvm.mips.extr.s.h(i64, i32) nounwind
46 %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 15)
50 declare i32 @llvm.mips.extr.rs.w(i64, i32) nounwind
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Ddsp-r1.ll6 ; CHECK: extr.w
8 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 15)
12 declare i32 @llvm.mips.extr.w(i64, i32) nounwind
18 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 %a1)
26 %1 = tail call i32 @llvm.mips.extr.r.w(i64 %a0, i32 15)
30 declare i32 @llvm.mips.extr.r.w(i64, i32) nounwind
36 %1 = tail call i32 @llvm.mips.extr.s.h(i64 %a0, i32 %a1)
40 declare i32 @llvm.mips.extr.s.h(i64, i32) nounwind
46 %1 = tail call i32 @llvm.mips.extr.rs.w(i64 %a0, i32 15)
50 declare i32 @llvm.mips.extr.rs.w(i64, i32) nounwind
[all …]
/external/llvm/test/MC/Mips/micromips-dsp/
Dvalid.s21 extr.w $27, $ac3, 31 # CHECK: extr.w $27, $ac3, 31 # encoding: [0x03,0x7f,0xce,0x7c]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/micromips-dsp/
Dvalid.s21 extr.w $27, $ac3, 31 # CHECK: extr.w $27, $ac3, 31 # encoding: [0x03,0x7f,0xce,0x7c]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/micromips-dspr2/
Dvalid.s34 extr.w $27, $ac3, 31 # CHECK: extr.w $27, $ac3, 31 # encoding: [0x03,0x7f,0xce,0x7c]

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