Searched refs:fcfid (Results 1 – 25 of 32) sorted by relevance
12
| /external/llvm/test/CodeGen/PowerPC/ |
| D | i64_fp.ll | 1 ; fcfid and fctid should be generated when the 64bit feature is enabled, but not
5 ; RUN: grep fcfid
9 ; RUN: grep fcfid
13 ; RUN: not grep fcfid
17 ; RUN: not grep fcfid
|
| D | fast-isel-conversion.ll | 29 ; PPC970: fcfid
54 ; PPC970: fcfid
78 ; PPC970: fcfid
102 ; PPC970: fcfid
119 ; ELF64: fcfid
124 ; ELF64LE: fcfid
127 ; PPC970: fcfid
141 ; ELF64: fcfid
144 ; ELF64LE: fcfid
147 ; PPC970: fcfid
[all …]
|
| D | fp-to-int-ext.ll | 15 ; CHECK: fcfid 1, [[REG1]]
28 ; CHECK: fcfid 1, [[REG1]]
46 ; CHECK: fcfid 1, [[REG4]]
64 ; CHECK: fcfid 1, [[REG4]]
|
| D | i32-to-float.ll | 17 ; CHECK: fcfid [[REG3:[0-9]+]], [[REG2]]
24 ; CHECK-PWR6: fcfid [[REG2:[0-9]+]], [[REG]]
50 ; CHECK: fcfid 1, [[REG2]]
56 ; CHECK-PWR6: fcfid 1, [[REG]]
62 ; CHECK-A2: fcfid 1, [[REG]]
|
| D | fp-to-int-to-fp.ll | 20 ; PPC64: fcfid [[REG2:[0-9]+]], [[REG1]]
34 ; FPCVT: fcfid 1, [[REG1]]
39 ; PPC64: fcfid 1, [[REG1]]
|
| D | fast-isel-conversion-p5.ll | 12 ; ELF64: fcfid
24 ; ELF64: fcfid
37 ; ELF64: fcfid
50 ; ELF64: fcfid
|
| D | no-extra-fp-conv-ldst.ll | 14 ; CHECK: fcfid 1, [[REG1]]
27 ; CHECK: fcfid 1, [[REG1]]
59 ; CHECK: fcfid 1, [[REG3]]
|
| D | fp2int2fp-ppcfp128.ll | 13 ; CHECK: fcfid
|
| D | qpx-bv-sint.ll | 23 ; CHECK: fcfid [[REG2:[0-9]+]], [[REG1]]
|
| D | i64-to-float.ll | 32 ; CHECK: fcfid 1, [[REG]]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | i64_fp.ll | 1 ; fcfid and fctid should be generated when the 64bit feature is enabled, but not
5 ; RUN: grep fcfid
9 ; RUN: grep fcfid
13 ; RUN: not grep fcfid
17 ; RUN: not grep fcfid
|
| D | fast-isel-conversion.ll | 26 ; PPC970: fcfid
44 ; PPC970: fcfid
64 ; PPC970: fcfid
85 ; PPC970: fcfid
104 ; CHECK: fcfid
107 ; PPC970: fcfid
121 ; CHECK: fcfid
124 ; PPC970: fcfid
138 ; CHECK: fcfid
142 ; PPC970: fcfid
[all …]
|
| D | fp-to-int-ext.ll | 15 ; CHECK: fcfid 1, [[REG1]]
28 ; CHECK: fcfid 1, [[REG1]]
46 ; CHECK: fcfid 1, [[REG4]]
64 ; CHECK: fcfid 1, [[REG4]]
|
| D | i32-to-float.ll | 17 ; CHECK: fcfid [[REG3:[0-9]+]], [[REG2]]
24 ; CHECK-PWR6: fcfid [[REG2:[0-9]+]], [[REG]]
50 ; CHECK: fcfid 1, [[REG2]]
56 ; CHECK-PWR6: fcfid 1, [[REG]]
62 ; CHECK-A2: fcfid 1, [[REG]]
|
| D | fast-isel-conversion-p5.ll | 12 ; ELF64: fcfid
24 ; ELF64: fcfid
37 ; ELF64: fcfid
50 ; ELF64: fcfid
|
| D | fp-to-int-to-fp.ll | 19 ; PPC64: fcfid [[REG2:[0-9]+]], [[REG1]]
37 ; PPC64: fcfid 1, [[REG1]]
|
| D | no-extra-fp-conv-ldst.ll | 14 ; CHECK: fcfid 1, [[REG1]]
27 ; CHECK: fcfid 1, [[REG1]]
|
| D | fp2int2fp-ppcfp128.ll | 13 ; CHECK: fcfid
|
| D | qpx-bv-sint.ll | 23 ; CHECK: fcfid [[REG2:[0-9]+]], [[REG1]]
|
| D | i64-to-float.ll | 42 ; CHECK: fcfid 1, [[REG]]
|
| /external/capstone/suite/MC/PowerPC/ |
| D | ppc64-encoding-fp.s.cs | 89 0xfc,0x40,0x1e,0x9c = fcfid 2, 3
90 0xfc,0x40,0x1e,0x9d = fcfid. 2, 3
|
| /external/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding-fp.s | 292 # CHECK-BE: fcfid 2, 3 # encoding: [0xfc,0x40,0x1e,0x9c]
293 # CHECK-LE: fcfid 2, 3 # encoding: [0x9c,0x1e,0x40,0xfc]
294 fcfid 2, 3
295 # CHECK-BE: fcfid. 2, 3 # encoding: [0xfc,0x40,0x1e,0x9d]
296 # CHECK-LE: fcfid. 2, 3 # encoding: [0x9d,0x1e,0x40,0xfc]
297 fcfid. 2, 3
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding-fp.s | 312 # CHECK-BE: fcfid 2, 3 # encoding: [0xfc,0x40,0x1e,0x9c]
313 # CHECK-LE: fcfid 2, 3 # encoding: [0x9c,0x1e,0x40,0xfc]
314 fcfid 2, 3
315 # CHECK-BE: fcfid. 2, 3 # encoding: [0xfc,0x40,0x1e,0x9d]
316 # CHECK-LE: fcfid. 2, 3 # encoding: [0x9d,0x1e,0x40,0xfc]
317 fcfid. 2, 3
|
| /external/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64-encoding-fp.txt | 264 # CHECK: fcfid 2, 3
267 # CHECK: fcfid. 2, 3
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64-encoding-fp.txt | 276 # CHECK: fcfid 2, 3
279 # CHECK: fcfid. 2, 3
|
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