| /external/capstone/suite/MC/PowerPC/ |
| D | ppc64-encoding-fp.s.cs | 85 0xfc,0x40,0x18,0x1e = fctiwz 2, 3
86 0xfc,0x40,0x18,0x1f = fctiwz. 2, 3
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | fast-isel-fpconv.ll | 3 ; The second fctiwz would use an incorrect input register due to wrong handling
13 ; CHECK: fctiwz {{[0-9]+}}, [[REG]]
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| D | 2008-10-28-f128-i32.ll | 95 ; CHECK-NEXT: fctiwz 0, 1
103 ; CHECK-NEXT: fctiwz 0, 0
215 ; CHECK-NEXT: fctiwz 0, 1
226 ; CHECK-NEXT: fctiwz 2, 2
270 ; CHECK-NEXT: fctiwz 0, 1
281 ; CHECK-NEXT: fctiwz 2, 2
|
| D | fp_to_uint.ll | 1 ; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=ppc32-- | grep fctiwz | count 1
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| D | stfiwx-2.ll | 8 ; CHECK: fctiwz 0, 1
|
| D | fast-isel-conversion-p5.ll | 62 ; ELF64: fctiwz
86 ; ELF64: fctiwz
|
| D | float-to-int.ll | 109 ; CHECK: fctiwz [[REG:[0-9]+]], 1
126 ; CHECK: fctiwz [[REG:[0-9]+]], 1
|
| D | fast-isel-conversion.ll | 326 ; CHECK: fctiwz
329 ; PPC970: fctiwz
359 ; CHECK: fctiwz
362 ; PPC970: fctiwz
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | fast-isel-fpconv.ll | 3 ; The second fctiwz would use an incorrect input register due to wrong handling
13 ; CHECK: fctiwz {{[0-9]+}}, [[REG]]
|
| D | no-extra-fp-conv-ldst.ll | 39 ; CHECK-DAG: fctiwz [[REG2:[0-9]+]], 1
55 ; CHECK-DAG: fctiwz [[REG2:[0-9]+]], 1
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| D | fp_to_uint.ll | 1 ; RUN: llc < %s -mattr=-vsx -march=ppc32 | grep fctiwz | count 1
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| D | fast-isel-conversion.ll | 385 ; ELF64: fctiwz
388 ; ELF64LE: fctiwz
391 ; PPC970: fctiwz
425 ; ELF64: fctiwz
428 ; ELF64LE: fctiwz
431 ; PPC970: fctiwz
|
| D | stfiwx-2.ll | 8 ; CHECK: fctiwz 0, 1
|
| D | fast-isel-conversion-p5.ll | 62 ; ELF64: fctiwz
86 ; ELF64: fctiwz
|
| D | float-to-int.ll | 80 ; CHECK: fctiwz [[REG:[0-9]+]], 1
97 ; CHECK: fctiwz [[REG:[0-9]+]], 1
|
| /external/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding-fp.s | 278 # CHECK-BE: fctiwz 2, 3 # encoding: [0xfc,0x40,0x18,0x1e]
279 # CHECK-LE: fctiwz 2, 3 # encoding: [0x1e,0x18,0x40,0xfc]
280 fctiwz 2, 3
281 # CHECK-BE: fctiwz. 2, 3 # encoding: [0xfc,0x40,0x18,0x1f]
282 # CHECK-LE: fctiwz. 2, 3 # encoding: [0x1f,0x18,0x40,0xfc]
283 fctiwz. 2, 3
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding-fp.s | 300 # CHECK-BE: fctiwz 2, 3 # encoding: [0xfc,0x40,0x18,0x1e]
301 # CHECK-LE: fctiwz 2, 3 # encoding: [0x1e,0x18,0x40,0xfc]
302 fctiwz 2, 3
303 # CHECK-BE: fctiwz. 2, 3 # encoding: [0xfc,0x40,0x18,0x1f]
304 # CHECK-LE: fctiwz. 2, 3 # encoding: [0x1f,0x18,0x40,0xfc]
305 fctiwz. 2, 3
|
| /external/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64-encoding-fp.txt | 252 # CHECK: fctiwz 2, 3
255 # CHECK: fctiwz. 2, 3
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64-encoding-fp.txt | 264 # CHECK: fctiwz 2, 3
267 # CHECK: fctiwz. 2, 3
|
| /external/v8/src/codegen/ppc/ |
| D | assembler-ppc.h | 967 void fctiwz(const DoubleRegister frt, const DoubleRegister frb);
|
| D | constants-ppc.h | 1561 V(fctiwz, FCTIWZ, 0xFC00001E) \
|
| D | assembler-ppc.cc | 1635 void Assembler::fctiwz(const DoubleRegister frt, const DoubleRegister frb) { in fctiwz() function in v8::internal::Assembler
|
| /external/v8/src/compiler/backend/ppc/ |
| D | code-generator-ppc.cc | 1881 __ fctiwz(kScratchDoubleReg, i.InputDoubleRegister(0)); in AssembleArchInstruction() local
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenAsmMatcher.inc | 4238 "fctiw\006fctiwu\007fctiwuz\006fctiwz\004fdiv\005fdivs\005fmadd\006fmadd"
5600 …{ 5871 /* fctiwz */, PPC::FCTIWZ, Convert__RegF8RC1_0__RegF8RC1_1, 0, { MCK_RegF8RC, MCK_RegF8RC }…
5601 …{ 5871 /* fctiwz */, PPC::FCTIWZo, Convert__RegF8RC1_1__RegF8RC1_2, 0, { MCK__DOT_, MCK_RegF8RC, M…
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 2108 "fctiwz", "$frD, $frB", IIC_FPGeneral,
|