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Searched refs:flat_load_dwordx4 (Results 1 – 25 of 42) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dload-global-f64.ll19 ; GCN-HSA: flat_load_dwordx4
30 ; GCN-HSA: flat_load_dwordx4
31 ; GCN-HSA: flat_load_dwordx4
43 ; GCN-HSA: flat_load_dwordx4
44 ; GCN-HSA: flat_load_dwordx4
58 ; GCN-HSA: flat_load_dwordx4
59 ; GCN-HSA: flat_load_dwordx4
60 ; GCN-HSA: flat_load_dwordx4
61 ; GCN-HSA: flat_load_dwordx4
79 ; GCN-HSA: flat_load_dwordx4
[all …]
Dload-global-i64.ll24 ; GCN-HSA: flat_load_dwordx4
38 ; GCN-HSA: flat_load_dwordx4
39 ; GCN-HSA: flat_load_dwordx4
54 ; GCN-HSA: flat_load_dwordx4
55 ; GCN-HSA: flat_load_dwordx4
72 ; GCN-HSA: flat_load_dwordx4
73 ; GCN-HSA: flat_load_dwordx4
74 ; GCN-HSA: flat_load_dwordx4
75 ; GCN-HSA: flat_load_dwordx4
98 ; GCN-HSA: flat_load_dwordx4
[all …]
Dload-global-i32.ll33 ; GCN-HSA: flat_load_dwordx4
45 ; GCN-HSA: flat_load_dwordx4
58 ; GCN-HSA: flat_load_dwordx4
59 ; GCN-HSA: flat_load_dwordx4
76 ; GCN-HSA: flat_load_dwordx4
77 ; GCN-HSA: flat_load_dwordx4
78 ; GCN-HSA: flat_load_dwordx4
79 ; GCN-HSA: flat_load_dwordx4
187 ; GCN-HSA: flat_load_dwordx4
199 ; GCN-HSA: flat_load_dwordx4
[all …]
Dload-global-f32.ll34 ; GCN-HSA: flat_load_dwordx4
46 ; GCN-HSA: flat_load_dwordx4
59 ; GCN-HSA: flat_load_dwordx4
60 ; GCN-HSA: flat_load_dwordx4
77 ; GCN-HSA: flat_load_dwordx4
78 ; GCN-HSA: flat_load_dwordx4
79 ; GCN-HSA: flat_load_dwordx4
80 ; GCN-HSA: flat_load_dwordx4
Dload-global-i16.ll60 ; GCN-HSA: flat_load_dwordx4
74 ; GCN-HSA: flat_load_dwordx4
75 ; GCN-HSA: flat_load_dwordx4
87 ; GCN-HSA: flat_load_dwordx4
88 ; GCN-HSA: flat_load_dwordx4
284 ; GCN-HSA: flat_load_dwordx4
318 ; GCN-HSA: flat_load_dwordx4
354 ; GCN-HSA: flat_load_dwordx4
355 ; GCN-HSA: flat_load_dwordx4
383 ; GCN-HSA: flat_load_dwordx4
[all …]
Dsalu-to-valu.ll157 ; GCN-HSA: flat_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
190 ; GCN-HSA: flat_load_dwordx4
191 ; GCN-HSA: flat_load_dwordx4
227 ; GCN-HSA: flat_load_dwordx4
228 ; GCN-HSA: flat_load_dwordx4
229 ; GCN-HSA: flat_load_dwordx4
230 ; GCN-HSA: flat_load_dwordx4
291 ; GCN-HSA: flat_load_dwordx4
292 ; GCN-HSA: flat_load_dwordx4
314 ; GCN-HSA: flat_load_dwordx4
[all …]
Dinline-constraints.ll8 ; GCN: flat_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
9 ; GCN: flat_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
22 …%v4_32 = tail call <4 x i32> asm sideeffect "flat_load_dwordx4 $0, $1", "=v,v"(i32 addrspace(1)* %…
23 %v128 = tail call i128 asm sideeffect "flat_load_dwordx4 $0, $1", "=v,v"(i32 addrspace(1)* %ptr)
Dvectorize-global-local.ll2 ; CHECK-DAG: flat_load_dwordx4
3 ; CHECK-DAG: flat_load_dwordx4
4 ; CHECK-DAG: flat_load_dwordx4
5 ; CHECK-DAG: flat_load_dwordx4
Dhalf.ll243 ; GCN: flat_load_dwordx4 [[TMP:v\[[0-9]+:[0-9]+\]]]
308 ; GCN: flat_load_dwordx4
309 ; GCN: flat_load_dwordx4
475 ; GCN: flat_load_dwordx4
491 ; GCN: flat_load_dwordx4
508 ; GCN: flat_load_dwordx4
509 ; GCN: flat_load_dwordx4
536 ; GCN: flat_load_dwordx4
537 ; GCN: flat_load_dwordx4
538 ; GCN: flat_load_dwordx4
[all …]
Dmesa_regression.ll4 ; CHECK: flat_load_dwordx4
/external/llvm/test/CodeGen/AMDGPU/
Dload-global-f64.ll19 ; GCN-HSA: flat_load_dwordx4
30 ; GCN-HSA: flat_load_dwordx4
31 ; GCN-HSA: flat_load_dwordx4
43 ; GCN-HSA: flat_load_dwordx4
44 ; GCN-HSA: flat_load_dwordx4
58 ; GCN-HSA: flat_load_dwordx4
59 ; GCN-HSA: flat_load_dwordx4
60 ; GCN-HSA: flat_load_dwordx4
61 ; GCN-HSA: flat_load_dwordx4
79 ; GCN-HSA: flat_load_dwordx4
[all …]
Dload-global-i64.ll24 ; GCN-HSA: flat_load_dwordx4
38 ; GCN-HSA: flat_load_dwordx4
39 ; GCN-HSA: flat_load_dwordx4
54 ; GCN-HSA: flat_load_dwordx4
55 ; GCN-HSA: flat_load_dwordx4
72 ; GCN-HSA: flat_load_dwordx4
73 ; GCN-HSA: flat_load_dwordx4
74 ; GCN-HSA: flat_load_dwordx4
75 ; GCN-HSA: flat_load_dwordx4
98 ; GCN-HSA: flat_load_dwordx4
[all …]
Dload-global-i32.ll33 ; GCN-HSA: flat_load_dwordx4
45 ; GCN-HSA: flat_load_dwordx4
58 ; GCN-HSA: flat_load_dwordx4
59 ; GCN-HSA: flat_load_dwordx4
76 ; GCN-HSA: flat_load_dwordx4
77 ; GCN-HSA: flat_load_dwordx4
78 ; GCN-HSA: flat_load_dwordx4
79 ; GCN-HSA: flat_load_dwordx4
187 ; GCN-HSA: flat_load_dwordx4
199 ; GCN-HSA: flat_load_dwordx4
[all …]
Dload-global-f32.ll34 ; GCN-HSA: flat_load_dwordx4
46 ; GCN-HSA: flat_load_dwordx4
59 ; GCN-HSA: flat_load_dwordx4
60 ; GCN-HSA: flat_load_dwordx4
77 ; GCN-HSA: flat_load_dwordx4
78 ; GCN-HSA: flat_load_dwordx4
79 ; GCN-HSA: flat_load_dwordx4
80 ; GCN-HSA: flat_load_dwordx4
Dload-global-i16.ll60 ; GCN-HSA: flat_load_dwordx4
74 ; GCN-HSA: flat_load_dwordx4
75 ; GCN-HSA: flat_load_dwordx4
230 ; GCN-HSA: flat_load_dwordx4
240 ; GCN-HSA: flat_load_dwordx4
252 ; GCN-HSA: flat_load_dwordx4
253 ; GCN-HSA: flat_load_dwordx4
275 ; GCN-HSA: flat_load_dwordx4
276 ; GCN-HSA: flat_load_dwordx4
277 ; GCN-HSA: flat_load_dwordx4
[all …]
Dsalu-to-valu.ll157 ; GCN-HSA: flat_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
192 ; GCN-HSA: flat_load_dwordx4
193 ; GCN-HSA: flat_load_dwordx4
229 ; GCN-HSA: flat_load_dwordx4
230 ; GCN-HSA: flat_load_dwordx4
231 ; GCN-HSA: flat_load_dwordx4
232 ; GCN-HSA: flat_load_dwordx4
293 ; GCN-HSA: flat_load_dwordx4
294 ; GCN-HSA: flat_load_dwordx4
316 ; GCN-HSA: flat_load_dwordx4
[all …]
Dinline-constraints.ll7 ; GCN: flat_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
17 …%v128 = tail call <4 x i32> asm sideeffect "flat_load_dwordx4 $0, $1", "=v,v"(i32 addrspace(1)* %p…
Dflat-address-space.ll82 ; CHECK: flat_load_dwordx4
/external/llvm/test/MC/AMDGPU/
Dreg-syntax-extra.s105 flat_load_dwordx4 v[8:11], v[2*2-2:(3*3-6)] label
108 flat_load_dwordx4 v[8/2+4:11/2+6], v[2:3] label
111 flat_load_dwordx4 [v[8/2+4],v9,v[10],v[11/2+6]], v[2:3] label
Dmacro-examples.s9 flat_load_dwordx4 v[8 + (\iter * 4):8 + (\iter * 4) + 3], v[2:3]
Dflat.s164 flat_load_dwordx4 v[5:8], v[3:4] label
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dreg-syntax-extra.s105 flat_load_dwordx4 v[8:11], v[2*2-2:(3*3-6)] label
108 flat_load_dwordx4 v[8/2+4:11/2+6], v[2:3] label
111 flat_load_dwordx4 [v[8/2+4],v9,v[10],v[11/2+6]], v[2:3] label
Dmacro-examples.s9 flat_load_dwordx4 v[8 + (\iter * 4):8 + (\iter * 4) + 3], v[2:3]
Dflat.s99 flat_load_dwordx4 v[5:8], v[3:4] label
/external/llvm/lib/Target/AMDGPU/
DCIInstructions.td132 flat<0xe, 0x17>, "flat_load_dwordx4", VReg_128

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