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/external/llvm/test/MC/AArch64/
Dneon-max-min-pairwise.s85 fminp v10.4h, v15.4h, v22.4h
86 fminp v3.8h, v5.8h, v6.8h
87 fminp v10.2s, v15.2s, v22.2s
88 fminp v3.4s, v5.4s, v6.4s
89 fminp v17.2d, v13.2d, v2.2d
Dfullfp16-neon-neg.s180 fminp v10.4h, v15.4h, v22.4h
182 fminp v3.8h, v5.8h, v6.8h
Dneon-diagnostics.s1174 fminp v0.4s, v1.4s, v2.2d
1175 fminp v0.8h, v1.8h, v2.8h
2898 fminp s0, v1.4h
2899 fminp d31, v2.8h
2900 fminp b3, v2.2s
Darm64-advsimd.s323 fminp.2s v0, v0, v0
393 ; CHECK: fminp.2s v0, v0, v0 ; encoding: [0x00,0xf4,0xa0,0x2e]
458 fminp.4h v0, v0, v0
483 ; CHECK: fminp.4h v0, v0, v0 ; encoding: [0x00,0x34,0xc0,0x2e]
508 fminp.8h v0, v0, v0
533 ; CHECK: fminp.8h v0, v0, v0 ; encoding: [0x00,0x34,0xc0,0x6e]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-max-min-pairwise.s85 fminp v10.4h, v15.4h, v22.4h
86 fminp v3.8h, v5.8h, v6.8h
87 fminp v10.2s, v15.2s, v22.2s
88 fminp v3.4s, v5.4s, v6.4s
89 fminp v17.2d, v13.2d, v2.2d
Dfullfp16-neon-neg.s180 fminp v10.4h, v15.4h, v22.4h
182 fminp v3.8h, v5.8h, v6.8h
Dneon-diagnostics.s1179 fminp v0.4s, v1.4s, v2.2d
1180 fminp v0.8h, v1.8h, v2.8h
2838 fminp s0, v1.4h
2839 fminp d31, v2.8h
2840 fminp b3, v2.2s
Darm64-advsimd.s323 fminp.2s v0, v0, v0
393 ; CHECK: fminp.2s v0, v0, v0 ; encoding: [0x00,0xf4,0xa0,0x2e]
458 fminp.4h v0, v0, v0
483 ; CHECK: fminp.4h v0, v0, v0 ; encoding: [0x00,0x34,0xc0,0x2e]
508 fminp.8h v0, v0, v0
533 ; CHECK: fminp.8h v0, v0, v0 ; encoding: [0x00,0x34,0xc0,0x6e]
/external/capstone/suite/MC/AArch64/
Dneon-max-min-pairwise.s.cs29 0xea,0xf5,0xb6,0x2e = fminp v10.2s, v15.2s, v22.2s
30 0xa3,0xf4,0xa6,0x6e = fminp v3.4s, v5.4s, v6.4s
31 0xb1,0xf5,0xe2,0x6e = fminp v17.2d, v13.2d, v2.2d
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-fminv.ll5 ; CHECK: fminp s0, v0.2s
19 ; CHECK: fminp d0, v0.2d
Darm64-vmax.ll590 ;CHECK: fminp.2s
593 %tmp3 = call <2 x float> @llvm.aarch64.neon.fminp.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
599 ;CHECK: fminp.4s
602 %tmp3 = call <4 x float> @llvm.aarch64.neon.fminp.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
608 ;CHECK: fminp.2d
611 %tmp3 = call <2 x double> @llvm.aarch64.neon.fminp.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
615 declare <2 x float> @llvm.aarch64.neon.fminp.v2f32(<2 x float>, <2 x float>) nounwind readnone
616 declare <4 x float> @llvm.aarch64.neon.fminp.v4f32(<4 x float>, <4 x float>) nounwind readnone
617 declare <2 x double> @llvm.aarch64.neon.fminp.v2f64(<2 x double>, <2 x double>) nounwind readnone
/external/llvm/test/CodeGen/AArch64/
Darm64-fminv.ll5 ; CHECK: fminp s0, v0.2s
19 ; CHECK: fminp d0, v0.2d
Darm64-vmax.ll590 ;CHECK: fminp.2s
593 %tmp3 = call <2 x float> @llvm.aarch64.neon.fminp.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
599 ;CHECK: fminp.4s
602 %tmp3 = call <4 x float> @llvm.aarch64.neon.fminp.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
608 ;CHECK: fminp.2d
611 %tmp3 = call <2 x double> @llvm.aarch64.neon.fminp.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
615 declare <2 x float> @llvm.aarch64.neon.fminp.v2f32(<2 x float>, <2 x float>) nounwind readnone
616 declare <4 x float> @llvm.aarch64.neon.fminp.v4f32(<4 x float>, <4 x float>) nounwind readnone
617 declare <2 x double> @llvm.aarch64.neon.fminp.v2f64(<2 x double>, <2 x double>) nounwind readnone
/external/v8/src/codegen/arm64/
Dmacro-assembler-arm64.h276 V(fminp, Fminp) \
380 V(fminp, Fminp) \
Dassembler-arm64.h1609 void fminp(const VRegister& vd, const VRegister& vn, const VRegister& vm);
1612 void fminp(const VRegister& vd, const VRegister& vn);
/external/vixl/test/test-trace-reference/
Dlog-disasm2290 0x~~~~~~~~~~~~~~~~ 7ef0fb58 fminp d24, v26.2d
2291 0x~~~~~~~~~~~~~~~~ 7eb0fa27 fminp s7, v17.2s
2292 0x~~~~~~~~~~~~~~~~ 6ee3f677 fminp v23.2d, v19.2d, v3.2d
2293 0x~~~~~~~~~~~~~~~~ 2ea9f6bd fminp v29.2s, v21.2s, v9.2s
2294 0x~~~~~~~~~~~~~~~~ 6eb5f700 fminp v0.4s, v24.4s, v21.4s
Dlog-disasm-colour2290 0x~~~~~~~~~~~~~~~~ 7ef0fb58 fminp d24, v26.2d
2291 0x~~~~~~~~~~~~~~~~ 7eb0fa27 fminp s7, v17.2s
2292 0x~~~~~~~~~~~~~~~~ 6ee3f677 fminp v23.2d, v19.2d, v3.2d
2293 0x~~~~~~~~~~~~~~~~ 2ea9f6bd fminp v29.2s, v21.2s, v9.2s
2294 0x~~~~~~~~~~~~~~~~ 6eb5f700 fminp v0.4s, v24.4s, v21.4s
Dlog-cpufeatures-custom2289 0x~~~~~~~~~~~~~~~~ 7ef0fb58 fminp d24, v26.2d ### {FP, NEON} ###
2290 0x~~~~~~~~~~~~~~~~ 7eb0fa27 fminp s7, v17.2s ### {FP, NEON} ###
2291 0x~~~~~~~~~~~~~~~~ 6ee3f677 fminp v23.2d, v19.2d, v3.2d ### {FP, NEON} ###
2292 0x~~~~~~~~~~~~~~~~ 2ea9f6bd fminp v29.2s, v21.2s, v9.2s ### {FP, NEON} ###
2293 0x~~~~~~~~~~~~~~~~ 6eb5f700 fminp v0.4s, v24.4s, v21.4s ### {FP, NEON} ###
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc2641 __ fminp(d24, v26.V2D()); in GenerateTestSequenceNEONFP() local
2642 __ fminp(s7, v17.V2S()); in GenerateTestSequenceNEONFP() local
2643 __ fminp(v23.V2D(), v19.V2D(), v3.V2D()); in GenerateTestSequenceNEONFP() local
2644 __ fminp(v29.V2S(), v21.V2S(), v9.V2S()); in GenerateTestSequenceNEONFP() local
2645 __ fminp(v0.V4S(), v24.V4S(), v21.V4S()); in GenerateTestSequenceNEONFP() local
Dtest-cpu-features-aarch64.cc3273 TEST_FP_NEON(fminp_0, fminp(s0, v1.V2S()))
3274 TEST_FP_NEON(fminp_1, fminp(d0, v1.V2D()))
3275 TEST_FP_NEON(fminp_2, fminp(v0.V2S(), v1.V2S(), v2.V2S()))
3276 TEST_FP_NEON(fminp_3, fminp(v0.V4S(), v1.V4S(), v2.V4S()))
3277 TEST_FP_NEON(fminp_4, fminp(v0.V2D(), v1.V2D(), v2.V2D()))
3672 TEST_FP_NEON_NEONHALF(fminp_0, fminp(v0.V4H(), v1.V4H(), v2.V4H()))
3673 TEST_FP_NEON_NEONHALF(fminp_1, fminp(v0.V8H(), v1.V8H(), v2.V8H()))
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt609 # CHECK: fminp v29.2s, v28.2s, v25.2s
610 # CHECK: fminp v9.4s, v8.4s, v5.4s
611 # CHECK: fminp v11.2d, v10.2d, v7.2d
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt609 # CHECK: fminp v29.2s, v28.2s, v25.2s
610 # CHECK: fminp v9.4s, v8.4s, v5.4s
611 # CHECK: fminp v11.2d, v10.2d, v7.2d
/external/vixl/src/aarch64/
Dassembler-aarch64.h3582 void fminp(const VRegister& vd, const VRegister& vn, const VRegister& vm);
3585 void fminp(const VRegister& vd, const VRegister& vn);
Dsimulator-aarch64.cc4575 fminp(vf, rd, rn, rm); in VisitNEON3Same()
4774 SIM_FUNC(FMINP, fminp); in VisitNEON3SameFP16()
6387 fminp(vf, rd, rn); in VisitNEONScalarPairwise()
Dmacro-assembler-aarch64.h2637 V(fminp, Fminp) \
2780 V(fminp, Fminp) \

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