| /external/llvm/test/CodeGen/AArch64/ |
| D | floatdp_2source.ll | 27 ; CHECK: fnmul {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
55 ; CHECK: fnmul {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | floatdp_2source.ll | 27 ; CHECK: fnmul {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
55 ; CHECK: fnmul {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-fp-encoding.s | 136 fnmul h1, h2, h3
137 fnmul s1, s2, s3
138 fnmul d1, d2, d3 define
140 ; FP16: fnmul h1, h2, h3 ; encoding: [0x41,0x88,0xe3,0x1e]
142 ; NO-FP16-NEXT: fnmul h1, h2, h3
143 ; CHECK: fnmul s1, s2, s3 ; encoding: [0x41,0x88,0x23,0x1e]
144 ; CHECK: fnmul d1, d2, d3 ; encoding: [0x41,0x88,0x63,0x1e]
|
| D | basic-a64-diagnostics.s | 1633 fnmul d1, d9, s18 define
|
| D | basic-a64-instructions.s | 1898 fnmul s22, s23, s24
1917 fnmul d22, d23, d24
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | arm64-fp-encoding.s | 136 fnmul h1, h2, h3
137 fnmul s1, s2, s3
138 fnmul d1, d2, d3 define
140 ; FP16: fnmul h1, h2, h3 ; encoding: [0x41,0x88,0xe3,0x1e]
142 ; NO-FP16-NEXT: fnmul h1, h2, h3
143 ; CHECK: fnmul s1, s2, s3 ; encoding: [0x41,0x88,0x23,0x1e]
144 ; CHECK: fnmul d1, d2, d3 ; encoding: [0x41,0x88,0x63,0x1e]
|
| D | basic-a64-diagnostics.s | 1638 fnmul d1, d9, s18 define
|
| D | basic-a64-instructions.s | 1881 fnmul s22, s23, s24
1900 fnmul d22, d23, d24
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-scalar-fp.txt | 112 # FP16: fnmul h1, h2, h3
113 # CHECK: fnmul s1, s2, s3
114 # CHECK: fnmul d1, d2, d3
|
| D | basic-a64-instructions.txt | 1448 # CHECK: fnmul s22, s23, s2
1468 # CHECK: fnmul d22, d23, d24
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-scalar-fp.txt | 112 # FP16: fnmul h1, h2, h3
113 # CHECK: fnmul s1, s2, s3
114 # CHECK: fnmul d1, d2, d3
|
| D | basic-a64-instructions.txt | 1464 # CHECK: fnmul s22, s23, s2
1484 # CHECK: fnmul d22, d23, d24
|
| /external/vixl/test/aarch64/ |
| D | test-disasm-fp-aarch64.cc | 147 COMPARE(fnmul(h4, h5, h6), "fnmul h4, h5, h6"); in TEST()
148 COMPARE(fnmul(s7, s8, s9), "fnmul s7, s8, s9"); in TEST()
149 COMPARE(fnmul(d10, d11, d12), "fnmul d10, d11, d12"); in TEST()
|
| D | test-cpu-features-aarch64.cc | 633 TEST_FP(fnmul_0, fnmul(d0, d1, d2))
634 TEST_FP(fnmul_1, fnmul(s0, s1, s2))
3498 TEST_FP_FPHALF(fnmul_0, fnmul(h0, h1, h2))
|
| D | test-trace-aarch64.cc | 550 __ fnmul(d31, d19, d1); in GenerateTestSequenceFP() local
551 __ fnmul(s18, s3, s17); in GenerateTestSequenceFP() local
|
| D | test-simulator-aarch64.cc | 2916 DEFINE_TEST_FP_FP16(fnmul, 2Op, Basic)
|
| /external/capstone/suite/MC/AArch64/ |
| D | basic-a64-instructions.s.cs | 739 0xf6,0x8a,0x38,0x1e = fnmul s22, s23, s24
748 0xf6,0x8a,0x78,0x1e = fnmul d22, d23, d24
|
| /external/v8/src/codegen/arm64/ |
| D | macro-assembler-arm64.h | 384 V(fnmul, Fnmul) \
|
| D | assembler-arm64.h | 1637 void fnmul(const VRegister& vd, const VRegister& vn, const VRegister& vm);
|
| /external/v8/src/execution/arm64/ |
| D | simulator-arm64.h | 2077 LogicVRegister fnmul(VectorFormat vform, LogicVRegister dst,
|
| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.h | 2969 LogicVRegister fnmul(VectorFormat vform,
|
| D | assembler-aarch64.h | 2281 void fnmul(const VRegister& vd, const VRegister& vn, const VRegister& vm);
|
| D | macro-assembler-aarch64.h | 1558 fnmul(vd, vn, vm); in Fnmul()
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm | 474 0x~~~~~~~~~~~~~~~~ 1e618a7f fnmul d31, d19, d1
475 0x~~~~~~~~~~~~~~~~ 1e318872 fnmul s18, s3, s17
|
| D | log-disasm-colour | 474 0x~~~~~~~~~~~~~~~~ 1e618a7f fnmul d31, d19, d1
475 0x~~~~~~~~~~~~~~~~ 1e318872 fnmul s18, s3, s17
|