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/external/mesa3d/src/intel/tools/tests/gen4.5/
Dsend.asm3 send(16) 1 null<1>UW g0<8,8,1>UW 0x85a04800
7 send(8) 1 null<1>F g0<4>F 0x8650c400
9 send(8) 1 null<1>F g0<4>F 0x8640c400
11 send(8) 13 g0<1>F g0<4>F 0x053190ff
13 send(8) 14 g9<1>F g0<4>F 0x042150ff
15 send(8) 1 null<1>F g0<4>F 0x8680c400
17 send(16) 1 g4<1>UW g0<8,8,1>UW 0x02780001
19 send(16) 1 g4<1>UW g0<8,8,1>UW 0x02580001
21 send(8) 14 g3<1>UD g0<4>F 0x04211000
25 send(16) 1 g26<1>UW g0<8,8,1>UW 0x02382001
[all …]
/external/mesa3d/src/intel/tools/tests/gen4/
Dsend.asm5 send(16) 1 null<1>UW g0<8,8,1>UW 0x85a04800
7 send(8) 1 null<1>F g0<4>F 0x8650c400
9 send(8) 1 null<1>F g0<4>F 0x8640c400
11 send(8) 13 g0<1>F g0<4>F 0x053190ff
13 send(8) 14 g10<1>F g0<4>F 0x042150ff
15 send(8) 1 null<1>F g0<4>F 0x8680c400
17 send(16) 1 g4<1>UW g0<8,8,1>UW 0x02780001
19 send(16) 1 g4<1>UW g0<8,8,1>UW 0x02580001
21 send(8) 14 g3<1>UD g0<4>F 0x04211000
25 send(16) 1 g26<1>UW g0<8,8,1>UW 0x0238a001
[all …]
/external/mesa3d/src/intel/compiler/
Dtest_eu_validate.cpp120 #define g0 brw_vec8_grf(0, 0) macro
134 brw_ADD(p, g0, g0, g0); in TEST_P()
141 brw_MOV(p, g0, null); in TEST_P()
148 brw_ADD(p, g0, g0, null); in TEST_P()
156 gen6_math(p, g0, BRW_MATH_FUNCTION_SIN, null, null); in TEST_P()
158 gen4_math(p, g0, BRW_MATH_FUNCTION_SIN, 0, null, BRW_MATH_PRECISION_FULL); in TEST_P()
167 gen6_math(p, g0, BRW_MATH_FUNCTION_POW, g0, null); in TEST_P()
210 brw_MOV(p, g0, g0); in TEST_P()
238 brw_MOV(p, g0, g0); in TEST_P()
250 gen4_math(p, g0, BRW_MATH_FUNCTION_SIN, 0, g0, BRW_MATH_PRECISION_FULL); in TEST_P()
[all …]
Dtest_eu_compact.cpp179 struct brw_reg g0 = brw_vec8_grf(0, 0); in gen_ADD_GRF_GRF_GRF() local
183 brw_ADD(p, g0, g2, g4); in gen_ADD_GRF_GRF_GRF()
189 struct brw_reg g0 = brw_vec8_grf(0, 0); in gen_ADD_GRF_GRF_IMM() local
192 brw_ADD(p, g0, g2, brw_imm_f(1.0)); in gen_ADD_GRF_GRF_IMM()
198 struct brw_reg g0 = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D); in gen_ADD_GRF_GRF_IMM_d() local
201 brw_ADD(p, g0, g2, brw_imm_d(1)); in gen_ADD_GRF_GRF_IMM_d()
207 struct brw_reg g0 = brw_vec8_grf(0, 0); in gen_MOV_GRF_GRF() local
210 brw_MOV(p, g0, g2); in gen_MOV_GRF_GRF()
226 struct brw_reg g0 = brw_vec1_grf(0, 0); in gen_ADD_vec1_GRF_GRF_GRF() local
230 brw_ADD(p, g0, g2, g4); in gen_ADD_vec1_GRF_GRF_GRF()
[all …]
/external/libldac/src/
Dmdct_fixp_ldac.c35 INT32 g0, g1, g2, g3; in proc_mdct_core_ldac() local
52 g0 = mul_rsftrnd_ldac(-p_x[3*nsmpl/2-1-i], p_w[nsmpl/2+i], LDAC_Q_MDCT_WIN-shift); in proc_mdct_core_ldac()
54 a_work[p_p[i]] = g0 + g1; in proc_mdct_core_ldac()
56 g0 = mul_rsftrnd_ldac(p_x[i], p_w[i], LDAC_Q_MDCT_WIN-shift); in proc_mdct_core_ldac()
58 a_work[p_p[nsmpl/2+i]] = g0 + g1; in proc_mdct_core_ldac()
63 g0 = mul_lsftrnd_ldac(-p_x[3*nsmpl/2-1-i], p_w[nsmpl/2+i], LDAC_Q_MDCT_WIN-shift); in proc_mdct_core_ldac()
65 a_work[p_p[i]] = g0 + g1; in proc_mdct_core_ldac()
67 g0 = mul_lsftrnd_ldac(p_x[i], p_w[i], LDAC_Q_MDCT_WIN-shift); in proc_mdct_core_ldac()
69 a_work[p_p[nsmpl/2+i]] = g0 + g1; in proc_mdct_core_ldac()
84 g0 = mul_rsftrnd_ldac(a_work[index1], p_c[coef], LDAC_Q_MDCT_COS+1); in proc_mdct_core_ldac()
[all …]
/external/libyuv/files/unit_test/
Dcolor_test.cc351 int r0, g0, b0, r1, g1, b1; in TEST_F() local
354 YUVToRGBReference(240, 255, 0, &r0, &g0, &b0); in TEST_F()
356 EXPECT_EQ(255, g0); in TEST_F()
365 YUVToRGBReference(240, 0, 0, &r0, &g0, &b0); in TEST_F()
367 EXPECT_EQ(255, g0); in TEST_F()
376 YUVToRGBReference(i, 128, 128, &r0, &g0, &b0); in TEST_F()
379 EXPECT_NEAR(g0, g1, ERROR_G); in TEST_F()
382 YUVToRGBReference(i, 0, 0, &r0, &g0, &b0); in TEST_F()
385 EXPECT_NEAR(g0, g1, ERROR_G); in TEST_F()
388 YUVToRGBReference(i, 0, 255, &r0, &g0, &b0); in TEST_F()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Sparc/
Dsparc-synthetic-instructions.s57 ! CHECK: xnor %g1, %g0, %g2 ! encoding: [0x84,0x38,0x40,0x00]
59 ! CHECK: xnor %g1, %g0, %g1 ! encoding: [0x82,0x38,0x40,0x00]
62 ! CHECK: sub %g0, %g1, %g2 ! encoding: [0x84,0x20,0x00,0x01]
64 ! CHECK: sub %g0, %g1, %g1 ! encoding: [0x82,0x20,0x00,0x01]
85 ! CHECK: andcc %g2, %g1, %g0 ! encoding: [0x80,0x88,0x80,0x01]
87 ! CHECK: andcc %g2, 4, %g0 ! encoding: [0x80,0x88,0xa0,0x04]
102 ! CHECK: mov %g0, %g1 ! encoding: [0x82,0x10,0x00,0x00]
104 ! CHECK: stb %g0, [%g1+%g2] ! encoding: [0xc0,0x28,0x40,0x02]
106 ! CHECK: sth %g0, [%g1+%g2] ! encoding: [0xc0,0x30,0x40,0x02]
108 ! CHECK: st %g0, [%g1+%g2] ! encoding: [0xc0,0x20,0x40,0x02]
[all …]
/external/llvm/test/MC/Sparc/
Dsparc-synthetic-instructions.s57 ! CHECK: xnor %g1, %g0, %g2 ! encoding: [0x84,0x38,0x40,0x00]
59 ! CHECK: xnor %g1, %g0, %g1 ! encoding: [0x82,0x38,0x40,0x00]
62 ! CHECK: sub %g0, %g1, %g2 ! encoding: [0x84,0x20,0x00,0x01]
64 ! CHECK: sub %g0, %g1, %g1 ! encoding: [0x82,0x20,0x00,0x01]
85 ! CHECK: andcc %g2, %g1, %g0 ! encoding: [0x80,0x88,0x80,0x01]
87 ! CHECK: andcc %g2, 4, %g0 ! encoding: [0x80,0x88,0xa0,0x04]
102 ! CHECK: mov %g0, %g1 ! encoding: [0x82,0x10,0x00,0x00]
104 ! CHECK: stb %g0, [%g1+%g2] ! encoding: [0xc0,0x28,0x40,0x02]
106 ! CHECK: sth %g0, [%g1+%g2] ! encoding: [0xc0,0x30,0x40,0x02]
108 ! CHECK: st %g0, [%g1+%g2] ! encoding: [0xc0,0x20,0x40,0x02]
[all …]
/external/mesa3d/src/intel/tools/tests/gen5/
Dsend.asm3 send(8) 1 null<1>UW g0<8,8,1>UW 0x8c084c00
7 send(16) 1 null<1>UW g0<8,8,1>UW 0x94084800
9 send(8) 1 null<1>F g0<4>F 0x8a08c400
19 send(8) 14 g3<1>UD g0<4>F 0x04181000
21 send(8) 1 null<1>F g0<4>F 0x8808c400
31 send(8) 1 null<1>F g0<4>F 0x8c08c400
45 send(8) 1 null<1>UW g0<8,8,1>UW 0x90084c00
47 send(16) 1 null<1>UW g0<8,8,1>UW 0x9c084800
49 send(8) 1 null<1>F g0<4>F 0x1a084400
51 send(8) 1 null<1>F g0<4>F 0x9008c460
[all …]
/external/mesa3d/src/util/format/
Du_format_yuv.c52 float r, g0, g1, b; in util_format_r8g8_b8g8_unorm_unpack_rgba_float() local
58 g0 = ubyte_to_float((value >> 8) & 0xff); in util_format_r8g8_b8g8_unorm_unpack_rgba_float()
63 dst[1] = g0; /* g */ in util_format_r8g8_b8g8_unorm_unpack_rgba_float()
79 g0 = ubyte_to_float((value >> 8) & 0xff); in util_format_r8g8_b8g8_unorm_unpack_rgba_float()
84 dst[1] = g0; /* g */ in util_format_r8g8_b8g8_unorm_unpack_rgba_float()
106 uint8_t r, g0, g1, b; in util_format_r8g8_b8g8_unorm_unpack_rgba_8unorm() local
112 g0 = (value >> 8) & 0xff; in util_format_r8g8_b8g8_unorm_unpack_rgba_8unorm()
117 dst[1] = g0; /* g */ in util_format_r8g8_b8g8_unorm_unpack_rgba_8unorm()
133 g0 = (value >> 8) & 0xff; in util_format_r8g8_b8g8_unorm_unpack_rgba_8unorm()
138 dst[1] = g0; /* g */ in util_format_r8g8_b8g8_unorm_unpack_rgba_8unorm()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dbug27085.ll4 ; CHECK-LONG: call ##g0@GDPLT
5 ; CHECK-LONG-NOT: call g0@GDPLT
6 ; CHECK: call g0@GDPLT
7 ; CHECK-NOT: call ##g0@GDPLT
11 @g0 = internal thread_local global i32 0, align 4
16 store volatile i32 1, i32* @g0, align 4, !tbaa !1
23 %v0 = load volatile i32, i32* @g0, align 4, !tbaa !1
28 store volatile i32 0, i32* @g0, align 4, !tbaa !1
Dpacked-store.ll9 @g0 = common global %s.0 zeroinitializer, align 1
16 store i8 1, i8* getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 1), align 1
17 %v1 = load i16, i16* getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 2), align 1
19 store i16 %v2, i16* getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 2), align 1
25 %v5 = load i16, i16* getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 2), align 1
29 store i16 %v8, i16* getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 2), align 1
33 %v9 = load i16, i16* getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 2), align 1
37 store i16 %v12, i16* getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 2), align 1
Dstore-imm-large-stack.ll7 @g0 = external global [1024 x i8], align 8
18 %v3 = load i8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @g0, i32 0, i32 9), align 1
19 %v4 = load i8, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @g0, i32 0, i32 10), align 2
25 …%v5 = load i16, i16* bitcast (i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @g0, i32 0, i3…
27 …%v6 = load i32, i32* bitcast (i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @g0, i32 0, i3…
29 …%v7 = load i16, i16* bitcast (i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @g0, i32 0, i3…
31 …%v8 = load i16, i16* bitcast (i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @g0, i32 0, i3…
33 …%v9 = load i32, i32* bitcast (i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @g0, i32 0, i3…
35 …%v10 = load i16, i16* bitcast (i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @g0, i32 0, i…
37 …%v11 = load i32, i32* bitcast (i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @g0, i32 0, i…
[all …]
Dcommon-global-addr.ll4 @g0 = external global i32
9 ; CHECK: ##g0
10 ; CHECK-NOT: ##g0
11 %v0 = load i32, i32* @g0, align 1
13 store i32 %v1, i32* @g0, align 1
Daggressive_licm.ll9 @g0 = common global [4 x i16] zeroinitializer, align 8
15 call void @f1(i16* getelementptr inbounds ([4 x i16], [4 x i16]* @g0, i32 0, i32 0), i16* %v0) #0
21 %v3 = load i32, i32* bitcast ([4 x i16]* @g0 to i32*), align 8
25 …%v7 = load i32, i32* bitcast (i16* getelementptr inbounds ([4 x i16], [4 x i16]* @g0, i32 0, i32 2…
46 …store i16 %v14, i16* getelementptr inbounds ([4 x i16], [4 x i16]* @g0, i32 0, i32 0), align 8, !t…
47 …store i16 %v13, i16* getelementptr inbounds ([4 x i16], [4 x i16]* @g0, i32 0, i32 1), align 2, !t…
48 …store i16 %v12, i16* getelementptr inbounds ([4 x i16], [4 x i16]* @g0, i32 0, i32 2), align 4, !t…
49 …store i16 0, i16* getelementptr inbounds ([4 x i16], [4 x i16]* @g0, i32 0, i32 3), align 2, !tbaa…
55 …call void @f2(i16* getelementptr inbounds ([4 x i16], [4 x i16]* @g0, i32 0, i32 0), i16 signext %…
Dmem-ops-sub_i16_01.ll5 @g0 = unnamed_addr global i16 -32, align 2
10 %v0 = load i16, i16* @g0, align 1, !tbaa !4
17 store i16 %v6, i16* @g0, align 2, !tbaa !4
23 %v0 = load i16, i16* @g0, align 2, !tbaa !4
27 store i16 %v3, i16* @g0, align 2, !tbaa !4
29 %v4 = load i16, i16* @g0, align 2, !tbaa !4
Dmem-ops-sub_i16.ll5 @g0 = unnamed_addr global i16 -32, align 2
10 %v0 = load i16, i16* @g0, align 1, !tbaa !4
17 store i16 %v6, i16* @g0, align 2, !tbaa !4
23 %v0 = load i16, i16* @g0, align 2, !tbaa !4
27 store i16 %v3, i16* @g0, align 2, !tbaa !4
29 %v4 = load i16, i16* @g0, align 2, !tbaa !4
Dmem-ops-sub_01.ll5 @g0 = unnamed_addr global i8 112, align 1
10 %v0 = load i8, i8* @g0, align 1, !tbaa !4
17 store i8 %v6, i8* @g0, align 1, !tbaa !4
23 %v0 = load i8, i8* @g0, align 1, !tbaa !4
27 store i8 %v3, i8* @g0, align 1, !tbaa !4
29 %v4 = load i8, i8* @g0, align 1, !tbaa !4
Dmem-ops-sub.ll5 @g0 = unnamed_addr global i8 112, align 1
10 %v0 = load i8, i8* @g0, align 1, !tbaa !4
17 store i8 %v6, i8* @g0, align 1, !tbaa !4
23 %v0 = load i8, i8* @g0, align 1, !tbaa !4
27 store i8 %v3, i8* @g0, align 1, !tbaa !4
29 %v4 = load i8, i8* @g0, align 1, !tbaa !4
/external/clang/test/CodeGen/
Dconst-arithmetic.c6 extern struct { unsigned char a, b; } g0[];
7 void *g1[] = {g0 + -1, g0 + -23 };
8 void *g2[] = {g0 - 1, g0 - 23 };
Dbitfield-assign.c22 int g0();
26 if ((s.f0 = 3) != -1) g0(); in f0()
31 if ((s.f1 = 3) != 1) g0(); in f1()
36 if ((s.f2 = 3) != 3) g0(); in f2()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dloh.mir8 @g0 = external global i32
31 ; CHECK-NEXT: $x0 = ADRP target-flags(aarch64-page) @g0
33 $x0 = ADRP target-flags(aarch64-page) @g0
41 ; CHECK-NEXT: $x20 = ADRP target-flags(aarch64-page) @g0
42 ; CHECK-NEXT: $x3 = ADDXri $x20, target-flags(aarch64-pageoff) @g0
44 ; CHECK-NEXT: $x1 = ADRP target-flags(aarch64-page) @g0
45 ; CHECK-NEXT: $x1 = ADDXri $x1, target-flags(aarch64-pageoff) @g0
46 $x1 = ADRP target-flags(aarch64-page) @g0
48 $x1 = ADDXri $x1, target-flags(aarch64-pageoff) @g0, 0
49 $x20 = ADRP target-flags(aarch64-page) @g0
[all …]
/external/tensorflow/tensorflow/python/ops/
Dop_selector_test.py52 g0 = ops_lib.Graph()
53 with g0.as_default():
66 self.assertEqual(op_selector.get_unique_graph([a0, b0]), g0)
86 g0 = ops_lib.Graph()
87 with g0.as_default():
91 self.assertEqual(len(op_selector.make_list_of_op(g0)), 2)
97 g0 = ops_lib.Graph()
98 with g0.as_default():
103 self.assertEqual(len(op_selector.make_list_of_t(g0)), 3)
113 g0 = ops_lib.Graph()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dmno-ldc1-sdc1.ll62 @g0 = common global double 0.000000e+00, align 8
81 ; 32R1-LE-STATIC-DAG: lui $[[R0:[0-9]+]], %hi(g0)
82 ; 32R1-LE-STATIC-DAG: lw $[[R1:[0-9]+]], %lo(g0)($[[R0]])
83 ; 32R1-LE-STATIC-DAG: addiu $[[R2:[0-9]+]], $[[R0]], %lo(g0)
88 ; 32R2-LE-STATIC-DAG: lui $[[R0:[0-9]+]], %hi(g0)
89 ; 32R2-LE-STATIC-DAG: lw $[[R1:[0-9]+]], %lo(g0)($[[R0]])
90 ; 32R2-LE-STATIC-DAG: addiu $[[R2:[0-9]+]], $[[R0]], %lo(g0)
95 ; 32R6-LE-STATIC-DAG: lui $[[R0:[0-9]+]], %hi(g0)
96 ; 32R6-LE-STATIC-DAG: lw $[[R1:[0-9]+]], %lo(g0)($[[R0]])
97 ; 32R6-LE-STATIC-DAG: addiu $[[R2:[0-9]+]], $[[R0]], %lo(g0)
[all …]
/external/llvm/test/CodeGen/Mips/
Dmno-ldc1-sdc1.ll62 @g0 = common global double 0.000000e+00, align 8
81 ; 32R1-LE-STATIC-DAG: lui $[[R0:[0-9]+]], %hi(g0)
82 ; 32R1-LE-STATIC-DAG: lw $[[R1:[0-9]+]], %lo(g0)($[[R0]])
83 ; 32R1-LE-STATIC-DAG: addiu $[[R2:[0-9]+]], $[[R0]], %lo(g0)
88 ; 32R2-LE-STATIC-DAG: lui $[[R0:[0-9]+]], %hi(g0)
89 ; 32R2-LE-STATIC-DAG: lw $[[R1:[0-9]+]], %lo(g0)($[[R0]])
90 ; 32R2-LE-STATIC-DAG: addiu $[[R2:[0-9]+]], $[[R0]], %lo(g0)
95 ; 32R6-LE-STATIC-DAG: lui $[[R0:[0-9]+]], %hi(g0)
96 ; 32R6-LE-STATIC-DAG: lw $[[R1:[0-9]+]], %lo(g0)($[[R0]])
97 ; 32R6-LE-STATIC-DAG: addiu $[[R2:[0-9]+]], $[[R0]], %lo(g0)
[all …]

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