/external/mesa3d/src/intel/tools/tests/gen7.5/ |
D | shr.asm | 8 shr(1) g29<1>UD g29<0,1,0>UD 5D { align1 WE_all 1N };
|
D | bfe.asm | 1 bfe(8) g31<1>UD g48<4,4,1>UD g64<4,4,1>UD g29<4,4,1>UD { align16 1Q };
|
D | mul.asm | 20 mul(8) g29<1>F g28<4>.yF 0x3000VF /* [0F, 1F, 0F, 0F]VF */ { align16 1Q }; 53 mul(8) g117<1>.yF g29<4>.xF g9<4>.xF { align16 NoDDChk 1Q };
|
D | add.asm | 40 add(8) g16<1>UD g29<0,1,0>UD g26<1,4,0>UW { align1 1Q }; 41 add(8) g17<1>UD g29<0,1,0>UD g26.2<1,4,0>UW { align1 2Q };
|
D | and.asm | 32 and.nz.f0.0(8) g29<1>UD g28<8,8,1>UD g27<8,8,1>UD { align1 1Q };
|
D | mad.asm | 27 mad(8) g17<1>.xF -g29<4,4,1>.xF g2.2<0,1,0>F g1.5<0,1,0>F { align16 NoDDClr 1Q };
|
D | sel.asm | 43 sel.ge(16) g29<1>F g27<8,8,1>F (abs)g17<8,8,1>F { align1 1H };
|
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Hexagon/ |
D | guest.s | 44 r1:0=g29:28 45 # CHECK: { r1:0 = g29:28 }
|
/external/mesa3d/src/intel/tools/tests/gen9/ |
D | mad.asm | 7 mad(16) g29<1>F -g33.0<0,1,0>F g25<4,4,1>F g15<4,4,1>F { align16 1H }; 8 mad(8) g29<1>DF g23<4,4,1>DF g27<4,4,1>DF -g25<4,4,1>DF { align16 1Q }; 36 mad(16) g27<1>F -g22<4,4,1>F (abs)g19<4,4,1>F g29.0<0,1,0>F { align16 1H };
|
D | cmp.asm | 29 cmp.ge.f0.0(8) g30<1>UD g29<8,8,1>UD g5.7<0,1,0>UD { align1 1Q }; 30 cmp.l.f0.0(8) g31<1>UD g29<8,8,1>UD g5.3<0,1,0>UD { align1 1Q }; 61 cmp.nz.f0.0(8) g29<1>D g22.1<8,4,2>D g3.2<0,1,0>D { align1 2Q };
|
D | send.asm | 125 send(8) null<1>F g29<8,8,1>F 0x0c0a0017 237 send(8) null<1>F g29<8,8,1>UD 0x0a0a8347 297 send(8) null<1>F g29<8,8,1>UD 0x08088147 829 send(8) null<1>F g29<8,8,1>UD 0x0a0a8167 967 send(8) null<1>F g29<8,8,1>UD 0x06088147 1029 send(8) g13<1>UD g29<8,8,1>UD 0x044a0218 1031 send(8) g17<1>UD g29<8,8,1>UD 0x044a0418 1033 send(8) g21<1>UD g29<8,8,1>UD 0x044a0618 1035 send(8) g25<1>UD g29<8,8,1>UD 0x044a0818 1073 send(8) null<1>F g29<8,8,1>UD 0x0c0a0337 [all …]
|
/external/mesa3d/src/intel/tools/tests/gen6/ |
D | not.asm | 1 not(8) g29<1>.xD g26<4>.xD { align16 1Q };
|
D | or.asm | 1 or(8) g29<1>UD g9<4>.xUD 0x00000014UD { align16 1Q };
|
/external/mesa3d/src/intel/tools/tests/gen7/ |
D | sel.asm | 50 (-f0.0) sel(8) g29<1>F (abs)g26<8,8,1>F 0x3f800000F /* 1F */ { align1 1Q }; 53 (-f0.0.x) sel(8) g32<1>.xF (abs)g29<4>.xF 0x3f800000F /* 1F */ { align16 1Q };
|
D | mul.asm | 15 mul(8) g29<1>F g28<4>.yF 0x3000VF /* [0F, 1F, 0F, 0F]VF */ { align16 1Q };
|
D | cmp.asm | 109 cmp.ge.f0.0(8) g30<1>.xyF (abs)g29<4>.xyyyF 0x5d5e0b6bF /* 1e+18F */ { align16 1Q }; 134 cmp.l.f0.0(16) null<1>D g32<8,8,1>UD g29<8,8,1>UD { align1 1H switch };
|
/external/clang/test/CodeGen/ |
D | const-init.c | 149 void g29() { in g29() function
|
/external/mesa3d/src/intel/tools/tests/gen8/ |
D | cmp.asm | 31 cmp.ge.f0.0(8) g30<1>UD g29<8,8,1>UD g5.7<0,1,0>UD { align1 1Q }; 32 cmp.l.f0.0(8) g31<1>UD g29<8,8,1>UD g5.3<0,1,0>UD { align1 1Q }; 59 cmp.nz.f0.0(8) g29<1>D g22.1<8,4,2>D g3.2<0,1,0>D { align1 2Q };
|
D | mad.asm | 6 mad(8) g29<1>DF g23<4,4,1>DF g27<4,4,1>DF -g25<4,4,1>DF { align16 1Q };
|
D | sendc.asm | 71 sendc(8) null<1>UW g29<8,8,1>F 0x0c0b0406
|
/external/mesa3d/src/intel/tools/tests/gen5/ |
D | mul.asm | 24 mul(8) g26<1>.wUD g29<4>.wF 0x45000000F /* 2048F */ { align16 NoDDChk };
|
/external/mesa3d/src/intel/tools/tests/gen4.5/ |
D | mul.asm | 17 mul(8) g26<1>.wUD g29<4>.wF 0x45000000F /* 2048F */ { align16 NoDDChk };
|
/external/mesa3d/src/intel/tools/tests/gen4/ |
D | mul.asm | 16 mul(8) g26<1>.wUD g29<4>.wF 0x45000000F /* 2048F */ { align16 NoDDChk };
|
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/ |
D | blockaddr-fpic.ll | 39 @g29 = private unnamed_addr constant [6 x i8] c"April\00", align 1 53 …i8]* @g28, i32 0, i32 0), i8* getelementptr inbounds ([6 x i8], [6 x i8]* @g29, i32 0, i32 0), i8*…
|
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
D | HexagonRegisterInfo.td | 245 def GPMUCNT3: Rg<29, "gpmucnt3", ["g29"]>, DwarfRegNum<[249]>; 265 def G29_28 : Rgg<28, "g29:28", [GPMUCNT2, GPMUCNT3]>, DwarfRegNum<[248]>;
|