| /external/mesa3d/src/gallium/drivers/r600/ |
| D | eg_asm.c | 226 int eg_bytecode_gds_build(struct r600_bytecode *bc, struct r600_bytecode_gds *gds, unsigned id) in eg_bytecode_gds_build() argument
228 unsigned gds_op = (r600_isa_fetch_opcode(bc->isa->hw_class, gds->op) >> 8) & 0x3f; in eg_bytecode_gds_build()
230 if (gds->op == FETCH_OP_TF_WRITE) { in eg_bytecode_gds_build()
237 S_SQ_MEM_GDS_WORD0_SRC_GPR(gds->src_gpr) | in eg_bytecode_gds_build()
238 S_SQ_MEM_GDS_WORD0_SRC_REL(gds->src_rel) | in eg_bytecode_gds_build()
239 S_SQ_MEM_GDS_WORD0_SRC_SEL_X(gds->src_sel_x) | in eg_bytecode_gds_build()
240 S_SQ_MEM_GDS_WORD0_SRC_SEL_Y(gds->src_sel_y) | in eg_bytecode_gds_build()
241 S_SQ_MEM_GDS_WORD0_SRC_SEL_Z(gds->src_sel_z); in eg_bytecode_gds_build()
243 bc->bytecode[id++] = S_SQ_MEM_GDS_WORD1_DST_GPR(gds->dst_gpr) | in eg_bytecode_gds_build()
244 S_SQ_MEM_GDS_WORD1_DST_REL(gds->dst_rel) | in eg_bytecode_gds_build()
[all …]
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| D | r600_asm.c | 61 list_inithead(&cf->gds); in r600_bytecode_cf()
97 struct r600_bytecode_gds *gds = CALLOC_STRUCT(r600_bytecode_gds); in r600_bytecode_gds() local
99 if (gds == NULL) in r600_bytecode_gds()
101 list_inithead(&gds->list); in r600_bytecode_gds()
102 return gds; in r600_bytecode_gds()
1491 int r600_bytecode_add_gds(struct r600_bytecode *bc, const struct r600_bytecode_gds *gds) in r600_bytecode_add_gds() argument
1498 memcpy(ngds, gds, sizeof(struct r600_bytecode_gds)); in r600_bytecode_add_gds()
1501 if (gds->uav_index_mode) in r600_bytecode_add_gds()
1502 egcm_load_index_reg(bc, gds->uav_index_mode - 1, false); in r600_bytecode_add_gds()
1516 list_addtail(&ngds->list, &bc->cf_last->gds); in r600_bytecode_add_gds()
[all …]
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| D | r600_asm.h | 210 struct list_head gds; member
293 int eg_bytecode_gds_build(struct r600_bytecode *bc, struct r600_bytecode_gds *gds, unsigned id);
311 const struct r600_bytecode_gds *gds);
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| D | r600_gpu_load.c | 92 UPDATE_COUNTER(gds, GDS_BUSY); in r600_update_mmio_counters()
212 return BUSY_INDEX(rscreen, gds); in busy_index_from_type()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | AMDGPUAsmGFX7.rst | 21 …src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
22 …src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
23 … :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
24 … :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
25 … src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
26 … src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
27 … src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
28 … src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
29 …src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
30 …src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
[all …]
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| D | AMDGPUAsmGFX8.rst | 21 … src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
22 …src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
23 …src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
24 …src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
25 … :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
26 … :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
27 … :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
28 … src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
29 … src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
30 … src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
[all …]
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| D | AMDGPUAsmGFX9.rst | 21 … src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
22 …src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
23 …src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
24 …src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
25 … :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
26 … :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
27 … :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
28 … src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
29 … src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
30 … src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
[all …]
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| /external/llvm/test/MC/AMDGPU/ |
| D | expressions.s | 5 .globl gds symbol
13 ds_gws_init v2 gds
17 s_mov_b32 s0, gds
22 s_mov_b32 s0, gds+4
|
| D | ds.s | 133 ds_gws_init v2 gds
137 ds_gws_sema_v v2 gds
141 ds_gws_sema_br v2 gds
145 ds_gws_sema_p v2 gds
149 ds_gws_barrier v2 gds
281 ds_ordered_count v8, v2 gds
|
| D | labels-branch.s | 13 s_branch gds
16 gds: label
|
| /external/mesa3d/src/gallium/drivers/r600/sfn/ |
| D | sfn_ir_to_assembly.cpp | 196 case Instruction::gds: in emit()
855 struct r600_bytecode_gds gds; in emit_gds() local
866 memset(&gds, 0, sizeof(struct r600_bytecode_gds)); in emit_gds()
868 gds.op = ds_opcode_map.at(instr.op()); in emit_gds()
869 gds.dst_gpr = instr.dest_sel(); in emit_gds()
870 gds.uav_id = (uav_idx >= 0 ? uav_idx : 0) + instr.uav_base(); in emit_gds()
871 gds.uav_index_mode = uav_idx >= 0 ? bim_none : bim_one; in emit_gds()
872 gds.src_gpr = instr.src_sel(); in emit_gds()
874 gds.src_sel_x = instr.src_swizzle(0); in emit_gds()
875 gds.src_sel_y = instr.src_swizzle(1); in emit_gds()
[all …]
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| D | sfn_instruction_base.h | 92 gds, enumerator
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| D | sfn_instruction_gds.cpp | 34 Instruction(gds), in GDSInstr()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/ |
| D | expressions.s | 5 .globl gds symbol
13 ds_gws_init v2 gds
17 s_mov_b32 s0, gds
22 s_mov_b32 s0, gds+4
|
| D | ds.s | 22 ds_add_src2_f32 v0 offset:4 gds
150 ds_gws_init v2 gds
154 ds_gws_init v3 offset:12345 gds
158 ds_gws_sema_v gds
162 ds_gws_sema_v offset:257 gds
166 ds_gws_sema_br v2 gds
170 ds_gws_sema_p gds
174 ds_gws_barrier v2 gds
315 ds_ordered_count v8, v2 gds
522 ds_swizzle_b32 v8, v2 gds
|
| D | labels-branch.s | 18 s_branch gds
23 gds: label
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | DSInstructions.td | 48 bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value
68 bits<1> gds;
86 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
87 "$addr, $data0$offset$gds"> {
106 (ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds),
107 "$addr, $data0, $data1"#"$offset"#"$gds"> {
126 offset0:$offset0, offset1:$offset1, gds:$gds),
127 "$addr, $data0, $data1$offset0$offset1$gds"> {
145 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
146 "$vdst, $addr, $data0$offset$gds"> {
[all …]
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| /external/mesa3d/src/gallium/drivers/r600/sb/ |
| D | sb_bc_dump.cpp | 480 unsigned gds = n.bc.op_ptr->flags & FF_GDS; in dump() local
481 bool gds_has_ret = gds && n.bc.op >= FETCH_OP_GDS_ADD_RET && in dump()
483 bool show_dst = !gds || (gds && gds_has_ret); in dump()
502 unsigned num_src_comp = gds ? 3 : vtx ? ctx.is_cayman() ? 2 : 1 : 4; in dump()
511 if (!gds) in dump()
514 if (gds) { in dump()
|
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_gfx_cs.c | 299 if (sctx->gds) { in si_add_gds_to_buffer_list()
300 sctx->ws->cs_add_buffer(sctx->gfx_cs, sctx->gds, RADEON_USAGE_READWRITE, 0, 0); in si_add_gds_to_buffer_list()
311 if (sctx->gds) in si_allocate_gds()
319 sctx->gds = ws->buffer_create(ws, 256, 4, RADEON_DOMAIN_GDS, RADEON_FLAG_DRIVER_INTERNAL); in si_allocate_gds()
322 assert(sctx->gds && sctx->gds_oa); in si_allocate_gds()
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| D | si_gpu_load.c | 89 UPDATE_COUNTER(gds, GDS_BUSY); in si_update_mmio_counters()
223 return BUSY_INDEX(sscreen, gds); in busy_index_from_type()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/ |
| D | ds_vi.txt | 84 # VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd9,0x00,0x02,0x00,0x00]
87 # VI: ds_gws_init v3 offset:12345 gds ; encoding: [0x39,0x30,0x33,0xd9,0x00,0x03,0x00,0x00]
90 # VI: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
93 # VI: ds_gws_sema_v offset:257 gds ; encoding: [0x01,0x01,0x35,0xd9,0x00,0x00,0x00,0x00]
96 # VI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x37,0xd9,0x00,0x02,0x00,0x00]
99 # VI: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
102 # VI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x3b,0xd9,0x00,0x02,0x00,0x00]
174 # VI: ds_swizzle_b32 v8, v2 gds ; encoding: [0x00,0x00,0x7b,0xd8,0x02,0x00,0x00,0x08]
327 # VI: ds_add_src2_f32 v0 offset:4 gds ; encoding: [0x04,0x00,0x2b,0xd9,0x00,0x00,0x00,0x00]
|
| /external/mesa3d/src/amd/compiler/ |
| D | aco_insert_waitcnt.cpp | 425 bool gds = static_cast<DS_instruction*>(instr)->gds; in check_instr() local
426 if ((it->second.events & lgkm_events) == (gds ? event_gds : event_lds)) in check_instr()
800 update_counters(ctx, ds->gds ? event_gds : event_lds, ds->sync); in gen()
801 if (ds->gds) in gen()
805 insert_wait_entry(ctx, instr->definitions[0], ds->gds ? event_gds : event_lds); in gen()
807 if (ds->gds) { in gen()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.td | 545 def gds : NamedOperandBit<"GDS", NamedMatchClass<"GDS">>;
2604 dag ins = (ins VGPR_32:$addr, offset:$offset, gds:$gds),
2605 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
2619 dag ins = (ins VGPR_32:$addr, offset:$offset, gds:$gds),
2620 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
2633 gds:$gds),
2634 string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> {
2646 dag ins = (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
2647 string asm = opName#" $addr, $data0"#"$offset$gds"> {
2661 offset0:$offset0, offset1:$offset1, gds:$gds),
[all …]
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| D | VIInstrFormats.td | 16 bits<1> gds;
25 let Inst{16} = gds;
|
| /external/llvm/test/MC/Disassembler/AMDGPU/ |
| D | ds_vi.txt | 84 # VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd8,0x02,0x00,0x00,0x00]
87 # VI: ds_gws_sema_v v2 gds ; encoding: [0x00,0x00,0x35,0xd8,0x02,0x00,0x00,0x00]
90 # VI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x37,0xd8,0x02,0x00,0x00,0x00]
93 # VI: ds_gws_sema_p v2 gds ; encoding: [0x00,0x00,0x39,0xd8,0x02,0x00,0x00,0x00]
96 # VI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x3b,0xd8,0x02,0x00,0x00,0x00]
195 # VI: ds_ordered_count v8, v2 gds ; encoding: [0x00,0x00,0x7f,0xd8,0x02,0x00,0x00,0x08]
|