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Searched refs:getAddressingMode (Results 1 – 25 of 39) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGAddressAnalysis.cpp89 if (N->getAddressingMode() == ISD::PRE_INC) { in match()
94 } else if (N->getAddressingMode() == ISD::PRE_DEC) { in match()
127 if (LSBase->getAddressingMode() == ISD::PRE_DEC || in match()
128 LSBase->getAddressingMode() == ISD::POST_DEC) in match()
DSelectionDAGDumper.cpp617 const char *AM = getIndexedModeName(LD->getAddressingMode()); in print_details()
629 const char *AM = getIndexedModeName(ST->getAddressingMode()); in print_details()
DLegalizeFloatTypes.cpp640 NewL = DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), NVT, dl, in SoftenFloatRes_LOAD()
652 NewL = DAG.getLoad(L->getAddressingMode(), ISD::NON_EXTLOAD, L->getMemoryVT(), in SoftenFloatRes_LOAD()
2111 SDValue newL = DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), IVT, in PromoteFloatRes_LOAD()
DTargetLowering.cpp3980 assert(LD->getAddressingMode() == ISD::UNINDEXED && in expandUnalignedLoad()
4134 assert(ST->getAddressingMode() == ISD::UNINDEXED && in expandUnalignedStore()
/external/OpenCL-CTS/test_conformance/spir/
Dkernelargs.h240 getAddressingMode() == Rhs->getAddressingMode() && in compare()
267 cl_addressing_mode getAddressingMode() const in getAddressingMode() function
Ddatagen.cpp233 cl_addressing_mode SamplerValuesGenerator::iterator::getAddressingMode() const in getAddressingMode() function in SamplerValuesGenerator::iterator
266 switch(getAddressingMode()) in toBitmap()
318 switch(getAddressingMode()) in toString()
Ddatagen.h550 cl_addressing_mode getAddressingMode() const;
/external/llvm/include/llvm/CodeGen/
DSelectionDAGNodes.h1784 assert(getAddressingMode() == AM && "MemIndexedMode encoding error!");
1793 ISD::MemIndexedMode getAddressingMode() const {
1798 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
1801 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2085 Ld->getAddressingMode() == ISD::UNINDEXED;
2115 cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
2123 St->getAddressingMode() == ISD::UNINDEXED;
2139 cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DSelectionDAGNodes.h2022 assert(getAddressingMode() == AM && "Value truncated");
2031 ISD::MemIndexedMode getAddressingMode() const {
2036 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2039 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2351 Ld->getAddressingMode() == ISD::UNINDEXED;
2381 cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
2389 St->getAddressingMode() == ISD::UNINDEXED;
2405 cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRISelDAGToDAG.cpp124 ISD::MemIndexedMode AM = LD->getAddressingMode(); in selectIndexedLoad()
171 ISD::MemIndexedMode AM = LD->getAddressingMode(); in selectIndexedProgMemLoad()
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp903 ? cast<LoadSDNode>(Op)->getAddressingMode() in SelectAddrMode2OffsetReg()
904 : cast<StoreSDNode>(Op)->getAddressingMode(); in SelectAddrMode2OffsetReg()
939 ? cast<LoadSDNode>(Op)->getAddressingMode() in SelectAddrMode2OffsetImmPre()
940 : cast<StoreSDNode>(Op)->getAddressingMode(); in SelectAddrMode2OffsetImmPre()
959 ? cast<LoadSDNode>(Op)->getAddressingMode() in SelectAddrMode2OffsetImm()
960 : cast<StoreSDNode>(Op)->getAddressingMode(); in SelectAddrMode2OffsetImm()
1038 ? cast<LoadSDNode>(Op)->getAddressingMode() in SelectAddrMode3Offset()
1039 : cast<StoreSDNode>(Op)->getAddressingMode(); in SelectAddrMode3Offset()
1134 ISD::MemIndexedMode AM = LdSt->getAddressingMode(); in SelectAddrMode6Offset()
1364 ? cast<LoadSDNode>(Op)->getAddressingMode() in SelectT2AddrModeImm8Offset()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp749 ? cast<LoadSDNode>(Op)->getAddressingMode() in SelectAddrMode2OffsetReg()
750 : cast<StoreSDNode>(Op)->getAddressingMode(); in SelectAddrMode2OffsetReg()
785 ? cast<LoadSDNode>(Op)->getAddressingMode() in SelectAddrMode2OffsetImmPre()
786 : cast<StoreSDNode>(Op)->getAddressingMode(); in SelectAddrMode2OffsetImmPre()
805 ? cast<LoadSDNode>(Op)->getAddressingMode() in SelectAddrMode2OffsetImm()
806 : cast<StoreSDNode>(Op)->getAddressingMode(); in SelectAddrMode2OffsetImm()
884 ? cast<LoadSDNode>(Op)->getAddressingMode() in SelectAddrMode3Offset()
885 : cast<StoreSDNode>(Op)->getAddressingMode(); in SelectAddrMode3Offset()
1007 ISD::MemIndexedMode AM = LdSt->getAddressingMode(); in SelectAddrMode6Offset()
1238 ? cast<LoadSDNode>(Op)->getAddressingMode() in SelectT2AddrModeImm8Offset()
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp509 const char *AM = getIndexedModeName(LD->getAddressingMode()); in print_details()
520 const char *AM = getIndexedModeName(ST->getAddressingMode()); in print_details()
DLegalizeFloatTypes.cpp636 NewL = DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), in SoftenFloatRes_LOAD()
649 NewL = DAG.getLoad(L->getAddressingMode(), ISD::NON_EXTLOAD, in SoftenFloatRes_LOAD()
2088 SDValue newL = DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), in PromoteFloatRes_LOAD()
DTargetLowering.cpp3245 assert(LD->getAddressingMode() == ISD::UNINDEXED && in expandUnalignedLoad()
3402 assert(ST->getAddressingMode() == ISD::UNINDEXED && in expandUnalignedStore()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td709 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
819 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
875 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
885 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
911 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
917 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
/external/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp520 ISD::MemIndexedMode AM = LD->getAddressingMode(); in SelectLoad()
628 ISD::MemIndexedMode AM = ST->getAddressingMode(); in SelectStore()
673 LD->getAddressingMode() != ISD::UNINDEXED) { in SelectMul()
702 LD->getAddressingMode() != ISD::UNINDEXED) { in SelectMul()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/
DTargetSelectionDAG.td645 // cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
646 // cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
993 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
1004 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
1035 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
1041 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/
DMSP430ISelDAGToDAG.cpp303 ISD::MemIndexedMode AM = LD->getAddressingMode(); in isValidIndexedLoad()
/external/llvm/lib/Target/MSP430/
DMSP430ISelDAGToDAG.cpp300 ISD::MemIndexedMode AM = LD->getAddressingMode(); in isValidIndexedLoad()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp453 ISD::MemIndexedMode AM = LD->getAddressingMode(); in SelectLoad()
563 ISD::MemIndexedMode AM = ST->getAddressingMode(); in SelectStore()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.td246 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
328 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp6517 assert(LD->getAddressingMode() == ISD::PRE_INC && in canReuseLoadAddress()
7988 assert(LN->getAddressingMode() == ISD::PRE_INC && in LowerVectorLoad()
7991 LN->getAddressingMode()); in LowerVectorLoad()
8082 assert(SN->getAddressingMode() == ISD::PRE_INC && in LowerVectorStore()
8085 SN->getAddressingMode()); in LowerVectorStore()
10724 assert(LD->getAddressingMode() == ISD::PRE_INC && in PerformDAGCombine()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp7130 assert(LD->getAddressingMode() == ISD::PRE_INC && in canReuseLoadAddress()
9249 assert(LN->getAddressingMode() == ISD::PRE_INC && in LowerVectorLoad()
9252 LN->getAddressingMode()); in LowerVectorLoad()
9341 assert(SN->getAddressingMode() == ISD::PRE_INC && in LowerVectorStore()
9344 SN->getAddressingMode()); in LowerVectorStore()
12644 assert(LD->getAddressingMode() == ISD::PRE_INC && in PerformDAGCombine()
/external/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp509 LD->getAddressingMode() != ISD::UNINDEXED || in isCalleeLoad()

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