Searched refs:getAllocatableSet (Results 1 – 16 of 16) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIFormMemoryClauses.cpp | 311 MaxVGPRs = TRI->getAllocatableSet(MF, &AMDGPU::VGPR_32RegClass).count(); in runOnMachineFunction()
312 MaxSGPRs = TRI->getAllocatableSet(MF, &AMDGPU::SGPR_32RegClass).count(); in runOnMachineFunction()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb1FrameLowering.cpp | 493 TRI->getAllocatableSet(MF, TRI->getRegClass(ARM::tGPRRegClassID)); in emitPopSpecialFixUp()
498 TRI->getAllocatableSet(MF, TRI->getRegClass(ARM::hGPRRegClassID)); in emitPopSpecialFixUp()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsDelaySlotFiller.cpp | 309 assert(MF.getSubtarget().getRegisterInfo()->getAllocatableSet(MF).test(R) && in addLiveInRegs()
365 BitVector AllocSet = TRI.getAllocatableSet(MF); in setUnallocatableRegs()
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| D | Mips16InstrInfo.cpp | 336 RI.getAllocatableSet in loadImmediate()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsDelaySlotFiller.cpp | 337 assert(MF.getSubtarget().getRegisterInfo()->getAllocatableSet(MF).test(R) && in addLiveInRegs()
393 BitVector AllocSet = TRI.getAllocatableSet(MF); in setUnallocatableRegs()
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| D | Mips16InstrInfo.cpp | 356 RI.getAllocatableSet in loadImmediate()
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| /external/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 155 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, in getAllocatableSet() function in TargetRegisterInfo
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| D | RegisterScavenging.cpp | 355 BitVector Candidates = TRI->getAllocatableSet(MF, RC); in scavengeRegister()
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| D | AggressiveAntiDepBreaker.cpp | 123 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]); in AggressiveAntiDepBreaker()
518 BitVector RCBV = TRI->getAllocatableSet(MF, RC); in GetRenameRegisters()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 135 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]); in AggressiveAntiDepBreaker()
537 BitVector RCBV = TRI->getAllocatableSet(MF, RC); in GetRenameRegisters()
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| D | TargetRegisterInfo.cpp | 217 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, in getAllocatableSet() function in TargetRegisterInfo
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| D | RegisterScavenging.cpp | 541 BitVector Candidates = TRI->getAllocatableSet(MF, RC); in scavengeRegister()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 354 BitVector getAllocatableSet(const MachineFunction &MF,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | Thumb1FrameLowering.cpp | 613 TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::tGPRRegClassID)); in emitPopSpecialFixUp()
624 TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::hGPRRegClassID)); in emitPopSpecialFixUp()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 365 BitVector getAllocatableSet(const MachineFunction &MF,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| D | AVRExpandPseudoInsts.cpp | 872 TRI->getAllocatableSet in scavengeGPR8()
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