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Searched refs:getRegClasses (Results 1 – 13 of 13) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DRegisterBankEmitter.cpp184 for (const auto &PossibleSubclass : RegisterClassHierarchy.getRegClasses()) { in visitRegisterBankClasses()
201 BitVector BV(RegisterClassHierarchy.getRegClasses().size()); in visitRegisterBankClasses()
221 (RegisterClassHierarchy.getRegClasses().size() + 31) / 32); in emitBaseClassImplementation()
253 << RegisterClassHierarchy.getRegClasses().size() << ");\n"; in emitBaseClassImplementation()
DRegisterInfoEmitter.cpp136 const auto &RegisterClasses = Bank.getRegClasses(); in runEnums()
197 unsigned NumRCs = RegBank.getRegClasses().size(); in EmitRegUnitPressure()
204 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure()
990 const auto &RegisterClasses = RegBank.getRegClasses(); in runMCDesc()
1143 const auto &RegisterClasses = RegBank.getRegClasses(); in runTargetHeader()
1179 const auto &RegisterClasses = RegBank.getRegClasses(); in runTargetDesc()
1590 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) { in debugDump()
1609 for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) { in debugDump()
DCodeGenRegisters.h696 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; } in getRegClasses() function
698 const std::list<CodeGenRegisterClass> &getRegClasses() const { in getRegClasses() function
DCodeGenTarget.cpp298 for (const auto &RC : getRegBank().getRegClasses()) { in getRegisterVTs()
313 for (const auto &RC : getRegBank().getRegClasses()) in ReadLegalValueTypes()
DCodeGenRegisters.cpp931 auto &RegClasses = RegBank.getRegClasses(); in computeSubClasses()
988 auto &RegClasses = RegBank.getRegClasses(); in getMatchingSubClassWithSubRegs()
1532 for (auto &RegClass : RegBank.getRegClasses()) { in computeUberSets()
1817 auto &RegClasses = getRegClasses(); in computeRegUnitSets()
2271 for (const auto &RC : getRegClasses()) { in getRegClassForRegister()
DDAGISelMatcherGen.cpp30 for (const auto &RC : T.getRegBank().getRegClasses()) { in getRegisterValueType()
DAsmMatcherEmitter.cpp1213 auto &RegClassList = Target.getRegBank().getRegClasses(); in buildRegisterClasses()
/external/llvm/utils/TableGen/
DRegisterInfoEmitter.cpp122 const auto &RegisterClasses = Bank.getRegClasses(); in runEnums()
192 unsigned NumRCs = RegBank.getRegClasses().size(); in EmitRegUnitPressure()
199 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure()
981 const auto &RegisterClasses = RegBank.getRegClasses(); in runMCDesc()
1138 const auto &RegisterClasses = RegBank.getRegClasses(); in runTargetHeader()
1174 const auto &RegisterClasses = RegBank.getRegClasses(); in runTargetDesc()
DCodeGenRegisters.h649 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; } in getRegClasses() function
651 const std::list<CodeGenRegisterClass> &getRegClasses() const { in getRegClasses() function
DCodeGenTarget.cpp246 for (const auto &RC : getRegBank().getRegClasses()) { in getRegisterVTs()
261 for (const auto &RC : getRegBank().getRegClasses()) in ReadLegalValueTypes()
DCodeGenRegisters.cpp851 auto &RegClasses = RegBank.getRegClasses(); in computeSubClasses()
1334 for (auto &RegClass : RegBank.getRegClasses()) { in computeUberSets()
1614 auto &RegClasses = getRegClasses(); in computeRegUnitSets()
2065 for (const auto &RC : getRegClasses()) { in getRegClassForRegister()
DDAGISelMatcherGen.cpp30 for (const auto &RC : T.getRegBank().getRegClasses()) { in getRegisterValueType()
DAsmMatcherEmitter.cpp1204 auto &RegClassList = Target.getRegBank().getRegClasses(); in buildRegisterClasses()