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Searched refs:getResNo (Results 1 – 25 of 61) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGPrinter.cpp69 std::advance(NI, I.getNode()->getOperand(I.getOperand()).getResNo()); in getEdgeTarget()
136 GW.emitEdge(nullptr, -1, G->getRoot().getNode(), G->getRoot().getResNo(), in addCustomGraphFeatures()
DInstrEmitter.cpp116 User->getOperand(2).getResNo() == ResNo) { in EmitCopyFromReg()
126 if (Op.getNode() != Node || Op.getResNo() != ResNo) in EmitCopyFromReg()
128 MVT VT = Node->getSimpleValueType(Op.getResNo()); in EmitCopyFromReg()
200 User->getOperand(2).getResNo() == ResNo) { in getDstOfOnlyCopyToRegUse()
248 User->getOperand(2).getResNo() == i) { in CreateVirtualRegisters()
289 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); in getVR()
715 SDValue Op = SDValue(Node, SD->getResNo()); in EmitDbgValue()
DResourcePriorityQueue.cpp130 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in numberRCValSuccInSU()
335 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in rawRegPressureDelta()
484 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in scheduledNode()
DSDNodeDbgValue.h101 unsigned getResNo() const { assert (kind==SDNODE); return u.s.ResNo; } in getResNo() function
DSelectionDAGAddressAnalysis.cpp124 if (LSBase->isIndexed() && Base.getResNo() == IndexResNo) in match()
DSelectionDAG.cpp438 ID.AddInteger(Op.getResNo()); in AddNodeIDOperands()
447 ID.AddInteger(Op.getResNo()); in AddNodeIDOperands()
2543 if (Op.getResNo() != 1) in computeKnownBits()
2672 if (ISD::isZEXTLoad(Op.getNode()) && Op.getResNo() == 0) { in computeKnownBits()
2729 if (Op.getResNo() == 1) { in computeKnownBits()
2778 if (Op.getResNo() == 1) { in computeKnownBits()
3082 if (N0.getOpcode() == ISD::UMUL_LOHI && N0.getResNo() == 1 && in computeOverflowKind()
3086 if (N1.getOpcode() == ISD::UMUL_LOHI && N1.getResNo() == 1) { in computeOverflowKind()
3358 if (Op.getResNo() != 1) in ComputeNumSignBits()
3561 if (Op.getResNo() == 0) { in ComputeNumSignBits()
[all …]
DScheduleDAGSDNodes.cpp122 unsigned ResNo = User->getOperand(2).getResNo(); in CheckForPhysRegDependency()
635 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency()
DLegalizeVectorOps.cpp210 return Result.getValue(Op.getResNo()); in TranslateLegalizeResults()
227 Op.getResNo()); in LegalizeOp()
697 return (Op.getResNo() ? NewChain : Value); in ExpandLoad()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGPrinter.cpp71 std::advance(NI, I.getNode()->getOperand(I.getOperand()).getResNo()); in getEdgeTarget()
138 GW.emitEdge(nullptr, -1, G->getRoot().getNode(), G->getRoot().getResNo(), in addCustomGraphFeatures()
DInstrEmitter.cpp116 User->getOperand(2).getResNo() == ResNo) { in EmitCopyFromReg()
126 if (Op.getNode() != Node || Op.getResNo() != ResNo) in EmitCopyFromReg()
128 MVT VT = Node->getSimpleValueType(Op.getResNo()); in EmitCopyFromReg()
199 User->getOperand(2).getResNo() == ResNo) { in getDstOfOnlyCopyToRegUse()
248 User->getOperand(2).getResNo() == i) { in CreateVirtualRegisters()
289 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); in getVR()
674 SDValue Op = SDValue(Node, SD->getResNo()); in EmitDbgValue()
DSDNodeDbgValue.h97 unsigned getResNo() const { assert (kind==SDNODE); return u.s.ResNo; } in getResNo() function
DResourcePriorityQueue.cpp134 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in numberRCValSuccInSU()
343 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in rawRegPressureDelta()
497 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in scheduledNode()
DSelectionDAG.cpp357 ID.AddInteger(Op.getResNo()); in AddNodeIDOperands()
367 ID.AddInteger(Op.getResNo()); in AddNodeIDOperands()
2130 if (Op.getResNo() != 1) in computeKnownBits()
2256 if (ISD::isZEXTLoad(Op.getNode()) && Op.getResNo() == 0) { in computeKnownBits()
2621 if (Op.getResNo() != 1) in ComputeNumSignBits()
2728 if (Op.getResNo() == 0) { in ComputeNumSignBits()
6274 assert(From->getNumValues() == 1 && FromN.getResNo() == 0 && in ReplaceAllUsesWith()
6368 setRoot(SDValue(To, getRoot().getResNo())); in ReplaceAllUsesWith()
6400 const SDValue &ToOp = To[Use.getResNo()]; in ReplaceAllUsesWith()
6412 setRoot(SDValue(To[getRoot().getResNo()])); in ReplaceAllUsesWith()
[all …]
DScheduleDAGSDNodes.cpp121 unsigned ResNo = User->getOperand(2).getResNo(); in CheckForPhysRegDependency()
634 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency()
DSelectionDAGBuilder.cpp763 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), in getCopyToRegs()
1024 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(), in resolveDanglingDebugInfo()
1428 SDValue(RetOp.getNode(), RetOp.getResNo() + i), in visitRet()
1466 SDValue(RetOp.getNode(), RetOp.getResNo() + j), in visitRet()
2835 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i)); in visitSelect()
2836 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i)); in visitSelect()
2838 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i), in visitSelect()
3230 SDValue(Agg.getNode(), Agg.getResNo() + i); in visitInsertValue()
3236 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); in visitInsertValue()
3241 SDValue(Agg.getNode(), Agg.getResNo() + i); in visitInsertValue()
[all …]
DLegalizeVectorOps.cpp183 return Result.getValue(Op.getResNo()); in TranslateLegalizeResults()
635 return (Op.getResNo() ? NewChain : Value); in ExpandLoad()
/external/llvm/utils/TableGen/
DDAGISelMatcherOpt.cpp52 CT->getResNo() == 0) // CheckChildType checks res #0 in ContractNodes()
363 CTM->getResNo() != 0 || in FactorNodes()
DDAGISelMatcher.cpp339 if (CT->getResNo() >= getOpcode().getNumResults()) in isContradictoryImpl()
342 MVT::SimpleValueType NodeType = getOpcode().getKnownType(CT->getResNo()); in isContradictoryImpl()
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DDAGISelMatcher.cpp338 if (CT->getResNo() >= getOpcode().getNumResults()) in isContradictoryImpl()
341 MVT::SimpleValueType NodeType = getOpcode().getKnownType(CT->getResNo()); in isContradictoryImpl()
DDAGISelMatcherOpt.cpp52 CT->getResNo() == 0) // CheckChildType checks res #0 in ContractNodes()
373 CTM->getResNo() != 0 || in FactorNodes()
DDAGISelMatcherEmitter.cpp500 if (cast<CheckTypeMatcher>(N)->getResNo() == 0) { in EmitMatcher()
505 OS << "OPC_CheckTypeRes, " << cast<CheckTypeMatcher>(N)->getResNo() in EmitMatcher()
/external/llvm/include/llvm/CodeGen/
DSelectionDAGNodes.h115 unsigned getResNo() const { return ResNo; }
205 (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo();
265 unsigned getResNo() const { return Val.getResNo(); }
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DSelectionDAGNodes.h135 unsigned getResNo() const { return ResNo; }
228 (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo();
290 unsigned getResNo() const { return Val.getResNo(); }
/external/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp1238 if (N.getResNo() != 0) break; in matchAddressRecursively()
1749 if (FlagUI.getUse().getResNo() != 1) continue; in hasNoSignedComparisonUses()
1804 if (StoredVal.getResNo() != 0) return false; in isLoadIncOrDecStore()
1858 if (UI.getUse().getResNo() != 0) in isLoadIncOrDecStore()
2515 (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) && in Select()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp1457 if (N.getResNo() != 0) break; in matchAddressRecursively()
2097 if (FlagUI.getUse().getResNo() != 1) continue; in hasNoSignedComparisonUses()
2149 if (UI.getUse().getResNo() != 1) in hasNoCarryFlagUses()
2161 if (FlagUI.getUse().getResNo() != 1) in hasNoCarryFlagUses()
2216 if (StoredVal.getResNo() != 0) return false; in isFusableLoadOpStorePattern()

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