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Searched refs:getSubRegs (Results 1 – 8 of 8) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td14 class getSubRegs<int size> {
174 def SGPR_64Regs : RegisterTuples<getSubRegs<2>.ret,
179 def SGPR_128Regs : RegisterTuples<getSubRegs<4>.ret,
186 def SGPR_256Regs : RegisterTuples<getSubRegs<8>.ret,
197 def SGPR_512Regs : RegisterTuples<getSubRegs<16>.ret,
222 def TTMP_64Regs : RegisterTuples<getSubRegs<2>.ret,
227 def TTMP_128Regs : RegisterTuples<getSubRegs<4>.ret,
233 def TTMP_256Regs : RegisterTuples<getSubRegs<8>.ret,
243 def TTMP_512Regs : RegisterTuples<getSubRegs<16>.ret,
263 list<SubRegIndex> indices = getSubRegs<size>.ret,
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/external/llvm/lib/Target/Hexagon/
DHexagonGenMux.cpp89 void getSubRegs(unsigned Reg, BitVector &SRs) const;
108 void HexagonGenMux::getSubRegs(unsigned Reg, BitVector &SRs) const { in getSubRegs() function in HexagonGenMux
116 getSubRegs(Reg, Set); in expandReg()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonGenMux.cpp128 void getSubRegs(unsigned Reg, BitVector &SRs) const;
147 void HexagonGenMux::getSubRegs(unsigned Reg, BitVector &SRs) const { in getSubRegs() function in HexagonGenMux
154 getSubRegs(Reg, Set); in expandReg()
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeGenRegisters.cpp1165 for (auto P : Reg.getSubRegs()) { in CodeGenRegBank()
1322 const CodeGenRegister::SubRegMap &SRM1 = Reg1.getSubRegs(); in computeComposites()
1330 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); in computeComposites()
1650 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs(); in normalizeWeight()
1986 const SubRegMap &SubRegs = Register.getSubRegs(); in computeRegUnitLaneMasks()
1992 if (!SubReg->getSubRegs().empty()) in computeRegUnitLaneMasks()
2115 const CodeGenRegister::SubRegMap &SRM = R->getSubRegs(); in inferSubClassWithSubReg()
2173 const CodeGenRegister *Sub = Super->getSubRegs().find(&SubIdx)->second; in inferMatchingSuperRegClass()
2328 const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs(); in computeCoveredRegisters()
DCodeGenRegisters.h182 const SubRegMap &getSubRegs() const { in getSubRegs() function
DRegisterInfoEmitter.cpp1633 for (std::pair<CodeGenSubRegIndex*,CodeGenRegister*> P : R.getSubRegs()) { in debugDump()
/external/llvm/utils/TableGen/
DCodeGenRegisters.cpp1127 const CodeGenRegister::SubRegMap &SRM1 = Reg1.getSubRegs(); in computeComposites()
1135 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); in computeComposites()
1448 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs(); in normalizeWeight()
1787 const SubRegMap &SubRegs = Register.getSubRegs(); in computeRegUnitLaneMasks()
1793 if (SubReg->getSubRegs().size() != 0) in computeRegUnitLaneMasks()
1916 const CodeGenRegister::SubRegMap &SRM = R->getSubRegs(); in inferSubClassWithSubReg()
1970 const CodeGenRegister *Sub = Super->getSubRegs().find(&SubIdx)->second; in inferMatchingSuperRegClass()
2122 const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs(); in computeCoveredRegisters()
DCodeGenRegisters.h156 const SubRegMap &getSubRegs() const { in getSubRegs() function