Searched refs:get_sysregs_ctx (Results 1 – 5 of 5) sorted by relevance
| /external/arm-trusted-firmware/services/std_svc/spm_mm/ |
| D | spm_mm_setup.c | 119 write_ctx_reg(get_sysregs_ctx(ctx), CTX_MAIR_EL1, in spm_sp_setup()
122 write_ctx_reg(get_sysregs_ctx(ctx), CTX_TCR_EL1, in spm_sp_setup()
125 write_ctx_reg(get_sysregs_ctx(ctx), CTX_TTBR0_EL1, in spm_sp_setup()
129 u_register_t sctlr_el1 = read_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1); in spm_sp_setup()
163 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1); in spm_sp_setup()
171 write_ctx_reg(get_sysregs_ctx(ctx), CTX_VBAR_EL1, in spm_sp_setup()
174 write_ctx_reg(get_sysregs_ctx(ctx), CTX_CNTKCTL_EL1, in spm_sp_setup()
184 write_ctx_reg(get_sysregs_ctx(ctx), CTX_CPACR_EL1, in spm_sp_setup()
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| /external/arm-trusted-firmware/lib/el3_runtime/aarch64/ |
| D | context_mgmt.c | 239 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); in cm_setup_context()
249 write_ctx_reg((get_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); in cm_setup_context()
341 sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx), in cm_prepare_el3_exit()
547 el1_sysregs_context_save(get_sysregs_ctx(ctx)); in cm_el1_sysregs_context_save()
564 el1_sysregs_context_restore(get_sysregs_ctx(ctx)); in cm_el1_sysregs_context_restore()
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| /external/arm-trusted-firmware/services/spd/trusty/ |
| D | trusty.c | 153 ctx->fiq_sp_el1 = read_ctx_reg(get_sysregs_ctx(handle), CTX_SP_EL1); in trusty_fiq_handler()
155 write_ctx_reg(get_sysregs_ctx(handle), CTX_SP_EL1, ctx->fiq_handler_sp); in trusty_fiq_handler()
214 write_ctx_reg(get_sysregs_ctx(handle), CTX_SP_EL1, ctx->fiq_sp_el1); in trusty_fiq_exit()
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| /external/arm-trusted-firmware/plat/nvidia/tegra/common/ |
| D | tegra_fiq_glue.c | 158 const el1_sys_regs_t *el1state_ctx = get_sysregs_ctx(ctx); in tegra_fiq_get_intr_context()
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| /external/arm-trusted-firmware/include/lib/el3_runtime/aarch64/ |
| D | context.h | 322 #define get_sysregs_ctx(h) (&((cpu_context_t *) h)->sysregs_ctx) macro
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