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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Damdgpu-codegenprepare-i16-to-i32.ll1092 ; SI: %r = add <3 x i15> %a, %b
1093 ; SI-NEXT: store volatile <3 x i15> %r
1094 ; VI: %[[A_32:[0-9]+]] = zext <3 x i15> %a to <3 x i32>
1095 ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i15> %b to <3 x i32>
1097 ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15>
1098 ; VI-NEXT: store volatile <3 x i15> %[[R_15]]
1099 define amdgpu_kernel void @add_3xi15(<3 x i15> %a, <3 x i15> %b) {
1100 %r = add <3 x i15> %a, %b
1101 store volatile <3 x i15> %r, <3 x i15> addrspace(1)* undef
1106 ; SI: %r = add nsw <3 x i15> %a, %b
[all …]
Damdgpu-codegenprepare-idiv.ll2101 define amdgpu_kernel void @udiv_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x, <3 x i15> %y) {
2103 ; CHECK-NEXT: [[TMP1:%.*]] = extractelement <3 x i15> [[X:%.*]], i64 0
2104 ; CHECK-NEXT: [[TMP2:%.*]] = extractelement <3 x i15> [[Y:%.*]], i64 0
2105 ; CHECK-NEXT: [[TMP3:%.*]] = zext i15 [[TMP1]] to i32
2106 ; CHECK-NEXT: [[TMP4:%.*]] = zext i15 [[TMP2]] to i32
2121 ; CHECK-NEXT: [[TMP19:%.*]] = trunc i32 [[TMP18]] to i15
2122 ; CHECK-NEXT: [[TMP20:%.*]] = insertelement <3 x i15> undef, i15 [[TMP19]], i64 0
2123 ; CHECK-NEXT: [[TMP21:%.*]] = extractelement <3 x i15> [[X]], i64 1
2124 ; CHECK-NEXT: [[TMP22:%.*]] = extractelement <3 x i15> [[Y]], i64 1
2125 ; CHECK-NEXT: [[TMP23:%.*]] = zext i15 [[TMP21]] to i32
[all …]
/external/llvm/test/Transforms/InstCombine/
Dapint-add1.ll22 define i15 @test3(i15 %x) {
23 %tmp.2 = xor i15 %x, 16384
25 %tmp.4 = add i15 %tmp.2, 16384
26 ret i15 %tmp.4
Dapint-xor1.ll15 define i15 @test2(i15 %x) {
16 %tmp.2 = xor i15 %x, 0
17 ret i15 %tmp.2
Dapint-and1.ll20 define i15 @test2(i15 %x) {
21 %tmp.2 = and i15 %x, -1 ; noop
22 ret i15 %tmp.2
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/XCore/
D2010-02-25-LSR-Crash.ll12 br i1 undef, label %bb3.i15.i.i, label %bb2
14 bb3.i15.i.i: ; preds = %bb3.i15.i.i, %entry
15 %indvar.i.i.i = phi i32 [ %indvar.next.i.i.i, %bb3.i15.i.i ], [ 0, %entry ] ; <i32> [#uses=2]
22 br label %bb3.i15.i.i
/external/llvm/test/CodeGen/XCore/
D2010-02-25-LSR-Crash.ll12 br i1 undef, label %bb3.i15.i.i, label %bb2
14 bb3.i15.i.i: ; preds = %bb3.i15.i.i, %entry
15 %indvar.i.i.i = phi i32 [ %indvar.next.i.i.i, %bb3.i15.i.i ], [ 0, %entry ] ; <i32> [#uses=2]
22 br label %bb3.i15.i.i
/external/llvm/test/CodeGen/X86/
Dx86-64-psub.ll25 %retval.0.extract.i15 = extractelement <1 x i64> %8, i32 0
26 ret i64 %retval.0.extract.i15
53 %retval.0.extract.i15 = extractelement <1 x i64> %8, i32 0
54 ret i64 %retval.0.extract.i15
82 %retval.0.extract.i15 = extractelement <1 x i64> %8, i32 0
83 ret i64 %retval.0.extract.i15
110 %retval.0.extract.i15 = extractelement <1 x i64> %8, i32 0
111 ret i64 %retval.0.extract.i15
138 %retval.0.extract.i15 = extractelement <1 x i64> %8, i32 0
139 ret i64 %retval.0.extract.i15
[all …]
D2009-07-20-DAGCombineBug.ll15 br i1 false, label %bb2.i16, label %bb1.i15
17 bb1.i15: ; preds = %bb3.i9
/external/llvm/test/Transforms/InstSimplify/
Dshift-knownbits.ll116 define <2 x i15> @shl_vector_zero(<2 x i15> %a, <2 x i15> %b) {
118 ; CHECK-NEXT: ret <2 x i15> %a
120 %and = and <2 x i15> %b, <i15 1024, i15 1024>
121 %shl = shl <2 x i15> %a, %and
122 ret <2 x i15> %shl
/external/llvm/test/tools/llvm-nm/X86/
Dradix.s116 .type i15,@object # @i15
117 .globl i15 symbol
119 i15: label
121 .size i15, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-nm/X86/
Dradix.s116 .type i15,@object # @i15
117 .globl i15 symbol
119 i15: label
121 .size i15, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dapint-xor1.ll15 define i15 @test2(i15 %x) {
16 %tmp.2 = xor i15 %x, 0
17 ret i15 %tmp.2
Dapint-and.ll15 define i15 @test2(i15 %x) {
17 ; CHECK-NEXT: ret i15 %x
19 %tmp.2 = and i15 %x, -1 ; noop
20 ret i15 %tmp.2
Dapint-add.ll27 define i15 @test3(i15 %x) {
29 ; CHECK-NEXT: ret i15 %x
31 %tmp.2 = xor i15 %x, 16384
32 %tmp.4 = add i15 %tmp.2, 16384
33 ret i15 %tmp.4
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dx86-64-psub.ll41 %retval.0.extract.i15 = extractelement <1 x i64> %8, i32 0
42 ret i64 %retval.0.extract.i15
75 %retval.0.extract.i15 = extractelement <1 x i64> %8, i32 0
76 ret i64 %retval.0.extract.i15
109 %retval.0.extract.i15 = extractelement <1 x i64> %8, i32 0
110 ret i64 %retval.0.extract.i15
143 %retval.0.extract.i15 = extractelement <1 x i64> %8, i32 0
144 ret i64 %retval.0.extract.i15
177 %retval.0.extract.i15 = extractelement <1 x i64> %8, i32 0
178 ret i64 %retval.0.extract.i15
[all …]
D2009-07-20-DAGCombineBug.ll15 br i1 false, label %bb2.i16, label %bb1.i15
17 bb1.i15: ; preds = %bb3.i9
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstSimplify/
Dshift-knownbits.ll116 define <2 x i15> @shl_vector_zero(<2 x i15> %a, <2 x i15> %b) {
118 ; CHECK-NEXT: ret <2 x i15> %a
120 %and = and <2 x i15> %b, <i15 1024, i15 1024>
121 %shl = shl <2 x i15> %a, %and
122 ret <2 x i15> %shl
/external/XNNPACK/src/f32-dwconv/gen/
Dup2x25-scalar.c62 const float* i15 = input[15]; in xnn_f32_dwconv_ukernel_up2x25__scalar() local
63 assert(i15 != NULL); in xnn_f32_dwconv_ukernel_up2x25__scalar()
226 const float vi15x0 = i15[0]; in xnn_f32_dwconv_ukernel_up2x25__scalar()
227 const float vi15x1 = i15[1]; in xnn_f32_dwconv_ukernel_up2x25__scalar()
228 i15 += 2; in xnn_f32_dwconv_ukernel_up2x25__scalar()
377 const float vi15 = *i15++; in xnn_f32_dwconv_ukernel_up2x25__scalar()
Dup2x25-scalar-acc2.c62 const float* i15 = input[15]; in xnn_f32_dwconv_ukernel_up2x25__scalar_acc2() local
63 assert(i15 != NULL); in xnn_f32_dwconv_ukernel_up2x25__scalar_acc2()
226 const float vi15x0 = i15[0]; in xnn_f32_dwconv_ukernel_up2x25__scalar_acc2()
227 const float vi15x1 = i15[1]; in xnn_f32_dwconv_ukernel_up2x25__scalar_acc2()
228 i15 += 2; in xnn_f32_dwconv_ukernel_up2x25__scalar_acc2()
380 const float vi15 = *i15++; in xnn_f32_dwconv_ukernel_up2x25__scalar_acc2()
Dup2x25-wasm-acc2.c62 const float* i15 = input[15]; in xnn_f32_dwconv_ukernel_up2x25__wasm_acc2() local
63 assert(i15 != NULL); in xnn_f32_dwconv_ukernel_up2x25__wasm_acc2()
226 const float vi15x0 = i15[0]; in xnn_f32_dwconv_ukernel_up2x25__wasm_acc2()
227 const float vi15x1 = i15[1]; in xnn_f32_dwconv_ukernel_up2x25__wasm_acc2()
228 i15 += 2; in xnn_f32_dwconv_ukernel_up2x25__wasm_acc2()
380 const float vi15 = *i15++; in xnn_f32_dwconv_ukernel_up2x25__wasm_acc2()
Dup2x25-wasm.c62 const float* i15 = input[15]; in xnn_f32_dwconv_ukernel_up2x25__wasm() local
63 assert(i15 != NULL); in xnn_f32_dwconv_ukernel_up2x25__wasm()
226 const float vi15x0 = i15[0]; in xnn_f32_dwconv_ukernel_up2x25__wasm()
227 const float vi15x1 = i15[1]; in xnn_f32_dwconv_ukernel_up2x25__wasm()
228 i15 += 2; in xnn_f32_dwconv_ukernel_up2x25__wasm()
377 const float vi15 = *i15++; in xnn_f32_dwconv_ukernel_up2x25__wasm()
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SimplifyCFG/
D2005-08-01-PHIUpdateFail.ll62 br i1 false, label %loopexit.0.i15, label %no_exit.0.i14
65 loopexit.0.i15: ; preds = %endif.1
67 no_exit.1.i16: ; preds = %no_exit.1.i16, %loopexit.0.i15
69 primal_start_artificial.exit: ; preds = %no_exit.1.i16, %loopexit.0.i15
/external/llvm/test/Transforms/SimplifyCFG/
D2005-08-01-PHIUpdateFail.ll62 br i1 false, label %loopexit.0.i15, label %no_exit.0.i14
65 loopexit.0.i15: ; preds = %endif.1
67 no_exit.1.i16: ; preds = %no_exit.1.i16, %loopexit.0.i15
69 primal_start_artificial.exit: ; preds = %no_exit.1.i16, %loopexit.0.i15
D2006-06-12-InfLoop.ll104 br i1 false, label %no_exit.i15.i.preheader, label %hamming.exit16.i
105 no_exit.i15.i.preheader: ; preds = %hamming.exit.i104
106 br label %no_exit.i15.i
107 no_exit.i15.i: ; preds = %no_exit.i15.i, %no_exit.i15.i.preheader
108 br i1 false, label %no_exit.i15.i, label %hamming.exit16.i.loopexit
109 hamming.exit16.i.loopexit: ; preds = %no_exit.i15.i
289 br i1 false, label %loopentry.3.i10.preheader, label %loopentry.4.i15
301 br i1 false, label %loopentry.3.i10, label %loopentry.4.i15.loopexit
302 loopentry.4.i15.loopexit: ; preds = %loopexit.3.i14
303 br label %loopentry.4.i15
[all …]

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