| /external/mesa3d/src/mesa/state_tracker/ |
| D | st_cb_compute.c | 42 GLintptr indirect_offset) in st_dispatch_compute_common() argument
67 info.indirect_offset = indirect_offset; in st_dispatch_compute_common()
80 GLintptr indirect_offset) in st_dispatch_compute_indirect() argument
85 st_dispatch_compute_common(ctx, NULL, NULL, indirect, indirect_offset); in st_dispatch_compute_indirect()
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| D | st_draw.c | 267 GLsizeiptr indirect_offset, in st_indirect_draw_vbo() argument
304 indirect.offset = indirect_offset; in st_indirect_draw_vbo()
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| /external/mesa3d/src/intel/compiler/ |
| D | brw_vec4_tcs.cpp | 160 const src_reg &indirect_offset) in emit_input_urb_read() argument
169 indirect_offset); in emit_input_urb_read()
182 if (inst->offset == 0 && indirect_offset.file == BAD_FILE) { in emit_input_urb_read()
195 const src_reg &indirect_offset) in emit_output_urb_read() argument
202 brw_imm_ud(dst.writemask << first_component), indirect_offset); in emit_output_urb_read()
222 const src_reg &indirect_offset) in emit_urb_write() argument
231 brw_imm_ud(writemask), indirect_offset); in emit_urb_write()
261 src_reg indirect_offset = get_indirect_offset(instr); in nir_emit_intrinsic() local
271 first_component, indirect_offset); in nir_emit_intrinsic()
279 src_reg indirect_offset = get_indirect_offset(instr); in nir_emit_intrinsic() local
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| D | brw_vec4_tcs.h | 62 const src_reg &indirect_offset);
66 const src_reg &indirect_offset);
69 unsigned base_offset, const src_reg &indirect_offset);
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| D | brw_vec4_tes.cpp | 160 src_reg indirect_offset = get_indirect_offset(instr); in nir_emit_intrinsic() local
165 if (indirect_offset.file != BAD_FILE) { in nir_emit_intrinsic()
173 retype(indirect_offset, BRW_REGISTER_TYPE_UD), in nir_emit_intrinsic()
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| D | brw_reg.h | 235 int indirect_offset:10; /* relative addressing offset */ member
442 reg.indirect_offset = 0; in brw_reg()
1146 reg.indirect_offset = offset; in brw_vec4_indirect()
1156 reg.indirect_offset = offset; in brw_vec1_indirect()
1167 reg.indirect_offset = offset; in brw_VxH_indirect()
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| D | brw_ir.h | 77 using brw_reg::indirect_offset;
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| D | brw_fs_nir.cpp | 2514 fs_reg indirect_offset = get_nir_src(offset_src); in emit_gs_input_load() local
2537 const fs_reg srcs[] = { icp_handle, indirect_offset }; in emit_gs_input_load()
2800 fs_reg indirect_offset = get_indirect_offset(instr); in nir_emit_tcs_intrinsic() local
2815 if (indirect_offset.file == BAD_FILE) { in nir_emit_tcs_intrinsic()
2832 const fs_reg srcs[] = { icp_handle, indirect_offset }; in nir_emit_tcs_intrinsic()
2858 if (inst->offset == 0 && indirect_offset.file == BAD_FILE) { in nir_emit_tcs_intrinsic()
2870 fs_reg indirect_offset = get_indirect_offset(instr); in nir_emit_tcs_intrinsic() local
2877 if (indirect_offset.file == BAD_FILE) { in nir_emit_tcs_intrinsic()
2906 const fs_reg srcs[] = { output_handles, indirect_offset }; in nir_emit_tcs_intrinsic()
2935 fs_reg indirect_offset = get_indirect_offset(instr); in nir_emit_tcs_intrinsic() local
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| /external/igt-gpu-tools/assembler/ |
| D | gen8_instruction.c | 77 gen8_set_dst_ida1_imm8(inst, (reg.dw1.bits.indirect_offset & IMM8_MASK)); in gen8_set_dst()
78 if ((reg.dw1.bits.indirect_offset & IMM9_MASK) == IMM9_MASK) in gen8_set_dst()
242 gen8_set_src0_ida1_imm8(inst, (reg.dw1.bits.indirect_offset & IMM8_MASK)); in gen8_set_src0()
243 if ((reg.dw1.bits.indirect_offset & IMM9_MASK) == IMM9_MASK) in gen8_set_src0()
330 gen8_set_src1_ida1_imm8(inst, (reg.dw1.bits.indirect_offset & IMM8_MASK)); in gen8_set_src1()
331 if ((reg.dw1.bits.indirect_offset & IMM9_MASK) == IMM9_MASK) in gen8_set_src1()
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| D | brw_reg.h | 129 int indirect_offset:10; /* relative addressing offset */ member
218 reg.dw1.bits.indirect_offset = 0; in brw_reg()
722 reg.dw1.bits.indirect_offset = offset; in brw_vec4_indirect()
732 reg.dw1.bits.indirect_offset = offset; in brw_vec1_indirect()
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| D | gram.y | 2343 $$.reg.dw1.bits.indirect_offset = $3.dw1.bits.indirect_offset;
2364 $$.dw1.bits.indirect_offset = $3;
2370 $$.dw1.bits.indirect_offset = 0;
2408 $$.dw1.bits.indirect_offset = $3.dw1.bits.indirect_offset;
2426 $$.dw1.bits.indirect_offset = $3.dw1.bits.indirect_offset;
2681 $$.reg.dw1.bits.indirect_offset = $1.dw1.bits.indirect_offset;
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| D | brw_eu_emit.c | 140 insn->bits1.ia1.dest_indirect_offset = dest.dw1.bits.indirect_offset; in brw_set_dest()
146 insn->bits1.ia16.dest_indirect_offset = dest.dw1.bits.indirect_offset; in brw_set_dest()
307 insn->bits2.ia1.src0_indirect_offset = reg.dw1.bits.indirect_offset; in brw_set_src0()
310 insn->bits2.ia16.src0_subreg_nr = reg.dw1.bits.indirect_offset; in brw_set_src0()
398 insn->bits3.ia1.src1_indirect_offset = reg.dw1.bits.indirect_offset; in brw_set_src1()
400 insn->bits3.ia16.src1_indirect_offset = reg.dw1.bits.indirect_offset / 16; in brw_set_src1()
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | brw_draw.c | 167 GLsizeiptr indirect_offset) in brw_emit_prim() argument
233 indirect_offset, 5 * sizeof(GLuint), false); in brw_emit_prim()
238 indirect_offset + 0); in brw_emit_prim()
240 indirect_offset + 4); in brw_emit_prim()
243 indirect_offset + 8); in brw_emit_prim()
246 indirect_offset + 12); in brw_emit_prim()
248 indirect_offset + 16); in brw_emit_prim()
251 indirect_offset + 12); in brw_emit_prim()
993 GLsizeiptr indirect_offset) in brw_draw_single_prim() argument
1058 indirect_offset + (is_indexed ? 12 : 8); in brw_draw_single_prim()
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| D | brw_draw.h | 77 GLsizeiptr indirect_offset,
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| /external/mesa3d/src/gallium/drivers/freedreno/ir3/ |
| D | ir3_const.h | 587 unsigned indirect_offset; in ir3_emit_cs_consts() local
597 if (info->indirect_offset & 0xf) { in ir3_emit_cs_consts()
601 indirect_offset = 0; in ir3_emit_cs_consts()
604 info->indirect_offset, 3); in ir3_emit_cs_consts()
607 indirect_offset = info->indirect_offset; in ir3_emit_cs_consts()
610 emit_const_prsc(ring, v, offset * 4, indirect_offset, 16, indirect); in ir3_emit_cs_consts()
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| /external/mesa3d/src/mesa/vbo/ |
| D | vbo_primitive_restart.c | 169 GLsizeiptr indirect_offset) in vbo_sw_primitive_restart() argument
201 indirect_offset); in vbo_sw_primitive_restart()
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| D | vbo.h | 240 GLsizeiptr indirect_offset);
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| /external/mesa3d/src/panfrost/midgard/ |
| D | midgard_compile.c | 1068 nir_src *indirect_offset, in emit_ubo_read() argument
1080 if (indirect_offset) { in emit_ubo_read()
1081 ins.src[2] = nir_src_index(ctx, indirect_offset); in emit_ubo_read()
1193 nir_src *indirect_offset, nir_alu_type type, bool flat) in emit_varying_read() argument
1220 if (indirect_offset) { in emit_varying_read()
1221 ins.src[2] = nir_src_index(ctx, indirect_offset); in emit_varying_read()
1520 nir_src *indirect_offset = direct ? NULL : src_offset; in emit_intrinsic() local
1531 …bo_read(ctx, &instr->instr, reg, (ctx->sysvals.sysval_count + offset) * 16, indirect_offset, 4, 0); in emit_intrinsic()
1539 emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, uindex); in emit_intrinsic()
1543 …emit_varying_read(ctx, reg, offset, nr_comp, component, indirect_offset, t | nir_dest_bit_size(ins… in emit_intrinsic()
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| /external/mesa3d/src/intel/tools/ |
| D | i965_gram.y | 1730 $$.indirect_offset = $3.indirect_offset;
1766 $$.indirect_offset = $2;
1798 $$.indirect_offset = $3.indirect_offset;
1817 $$.indirect_offset = $3.indirect_offset;
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| /external/mesa3d/src/gallium/drivers/freedreno/a5xx/ |
| D | fd5_compute.c | 216 OUT_RELOC(ring, rsc->bo, info->indirect_offset, 0, 0); /* ADDR_LO/HI */ in fd5_launch_grid()
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| /external/mesa3d/src/gallium/drivers/freedreno/a6xx/ |
| D | fd6_compute.c | 202 OUT_RELOC(ring, rsc->bo, info->indirect_offset, 0, 0); /* ADDR_LO/HI */ in fd6_launch_grid()
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| /external/mesa3d/src/gallium/drivers/softpipe/ |
| D | sp_compute.c | 153 info->indirect_offset, in fill_grid_size()
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| /external/mesa3d/src/gallium/drivers/nouveau/nvc0/ |
| D | nvc0_compute.c | 472 uint32_t offset = res->offset + info->indirect_offset; in nvc0_launch_grid()
512 uint32_t offset = res->offset + info->indirect_offset; in nvc0_compute_update_indirect_invocations()
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| /external/mesa3d/src/gallium/include/pipe/ |
| D | p_state.h | 895 unsigned indirect_offset; /**< must be 4 byte aligned */ member
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| /external/mesa3d/src/gallium/drivers/iris/ |
| D | iris_draw.c | 300 grid_ref->offset = grid->indirect_offset; in iris_update_grid_size_resource()
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