Searched refs:input_clk (Results 1 – 5 of 5) sorted by relevance
43 unsigned long input_clk; /* master clock (Hz) */ member60 priv->input_clk = IOBUS_FREQ; in uniphier_i2c_probe()186 writel((priv->input_clk / speed / 2 << 16) | (priv->input_clk / speed), in uniphier_i2c_set_bus_speed()
161 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk, in cdns_i2c_calc_divs() argument169 temp = input_clk / (22 * fscl); in cdns_i2c_calc_divs()180 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1)); in cdns_i2c_calc_divs()186 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1)); in cdns_i2c_calc_divs()
32 uint input_clk; /* Input clock to MMC controller */ member65 sysclk2 = host->input_clk;502 priv->input_clk = clk_get(DAVINCI_MMCSD_CLKID);
149 uint input_clk; /* Input clock to MMC controller */ member
349 mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID); in board_mmc_init()