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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SchedThunderX2T99.td401 def : InstRW<[THX2T99Write_1Cyc_I2], (instrs B, BL, BR, BLR)>;
402 def : InstRW<[THX2T99Write_1Cyc_I2], (instrs RET)>;
436 def : InstRW<[WriteI], (instrs COPY)>;
484 (instrs MOVKWi, MOVKXi, MOVNWi, MOVNXi, MOVZWi, MOVZXi)>;
487 (instrs ASRVWr, ASRVXr, LSLVWr, LSLVXr, RORVWr, RORVXr)>;
527 // (instrs MADDWrrr, MSUBWrrr)>;
528 def : InstRW<[WriteIM32], (instrs MADDWrrr, MSUBWrrr)>;
529 def : InstRW<[WriteIM32], (instrs MADDXrrr, MSUBXrrr)>;
533 def : InstRW<[WriteID32], (instrs SDIVWr, UDIVWr)>;
534 def : InstRW<[WriteID64], (instrs SDIVXr, UDIVXr)>;
[all …]
DAArch64SchedA57.td130 def : InstRW<[WriteI], (instrs COPY)>;
136 def : InstRW<[A57Write_1cyc_1B_1I], (instrs BL)>;
137 def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>;
153 def : InstRW<[A57Write_6cyc_1M], (instrs SMULHrr, UMULHrr)>;
159 def : InstRW<[A57Write_1cyc_1I], (instrs EXTRWrri)>;
160 def : InstRW<[A57Write_3cyc_1I_1M], (instrs EXTRXrri)>;
558 def : InstRW<[A57Write_32cyc_1W], (instrs FDIVDrr)>;
559 def : InstRW<[A57Write_17cyc_1W], (instrs FDIVSrr)>;
565 def : InstRW<[A57Write_32cyc_1W], (instrs FSQRTDr)>;
566 def : InstRW<[A57Write_17cyc_1W], (instrs FSQRTSr)>;
[all …]
DAArch64SchedFalkorDetails.td583 def : InstRW<[FalkorWr_1XYZ_1cyc], (instrs COPY)>;
600 def : InstRW<[FalkorWr_1VXVY_4cyc], (instrs FCVTXNv1i64)>;
606 (instrs FMULX32)>;
611 (instrs FMULX64)>;
617 def : InstRW<[FalkorWr_2VXVY_2cyc], (instrs FCVTLv4i16, FCVTLv2i32)>;
620 def : InstRW<[FalkorWr_1VX_1VY_10cyc],(instrs FDIVv2f32)>;
621 def : InstRW<[FalkorWr_1VX_1VY_12cyc],(instrs FSQRTv2f32)>;
626 def : InstRW<[FalkorWr_2VXVY_4cyc], (instrs FCVTLv8i16, FCVTLv4i32)>;
635 def : InstRW<[FalkorWr_3VXVY_4cyc], (instrs FCVTNv4i16, FCVTNv2i32, FCVTXNv2f32)>;
636 def : InstRW<[FalkorWr_3VXVY_5cyc], (instrs FCVTNv8i16, FCVTNv4i32, FCVTXNv4f32)>;
[all …]
DAArch64SchedKryoDetails.td100 (instrs SADDLVv4i32v, UADDLVv4i32v)>;
106 (instrs SADDLVv8i16v, UADDLVv8i16v)>;
112 (instrs SADDLVv16i8v, UADDLVv16i8v)>;
118 (instrs SADDLVv4i16v, UADDLVv4i16v, ADDVv4i16v)>;
124 (instrs SADDLVv8i8v, UADDLVv8i8v, ADDVv8i8v)>;
196 (instrs SMULHrr, UMULHrr)>;
340 (instrs ABSv1i64)>;
370 (instrs ADDv1i64)>;
394 (instrs ADDPv2i64p)>;
406 (instrs ADDVv4i32v)>;
[all …]
DAArch64SchedCyclone.td117 def : InstRW<[WriteImmZ], (instrs MOVZWi,MOVZXi,ANDWri,ANDXri)>;
128 def : InstRW<[WriteMov], (instrs COPY,ORRXrr,ADDXrr)>;
275 def : InstRW<[WriteST, WriteST], (instrs STPQi)>;
293 def : InstRW<[WriteI], (instrs ISB)>;
337 def : InstRW<[WriteVMov], (instrs ORRv16i8)>;
353 def : InstRW<[WriteLD], (instrs FMOVSWr,FMOVDXr,FMOVDXHighr)>;
434 def : InstRW<[CyWriteV4], (instrs FADDPv2i32p)>;
435 def : InstRW<[CyWriteV5], (instrs FADDPv2i64p)>;
442 def : InstRW<[CyWriteV4], (instrs FADDSrr,FADDv2f32,FADDv4f32,
446 def : InstRW<[CyWriteV5], (instrs FADDDrr,FADDv2f64,
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64SchedA57.td128 def : InstRW<[WriteI], (instrs COPY)>;
134 def : InstRW<[A57Write_1cyc_1B_1I], (instrs BL)>;
135 def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>;
151 def : InstRW<[A57Write_6cyc_1M], (instrs SMULHrr, UMULHrr)>;
157 def : InstRW<[A57Write_1cyc_1I], (instrs EXTRWrri)>;
158 def : InstRW<[A57Write_3cyc_1I_1M], (instrs EXTRXrri)>;
554 def : InstRW<[A57Write_32cyc_1X], (instrs FDIVDrr)>;
555 def : InstRW<[A57Write_18cyc_1X], (instrs FDIVSrr)>;
561 def : InstRW<[A57Write_32cyc_1X], (instrs FSQRTDr)>;
562 def : InstRW<[A57Write_18cyc_1X], (instrs FSQRTSr)>;
[all …]
DAArch64SchedKryoDetails.td100 (instrs SADDLVv4i32v, UADDLVv4i32v)>;
106 (instrs SADDLVv8i16v, UADDLVv8i16v)>;
112 (instrs SADDLVv16i8v, UADDLVv16i8v)>;
118 (instrs SADDLVv4i16v, UADDLVv4i16v, ADDVv4i16v)>;
124 (instrs SADDLVv8i8v, UADDLVv8i8v, ADDVv8i8v)>;
196 (instrs SMULHrr, UMULHrr)>;
340 (instrs ABSv1i64)>;
370 (instrs ADDv1i64)>;
394 (instrs ADDPv2i64p)>;
406 (instrs ADDVv4i32v)>;
[all …]
DAArch64SchedCyclone.td115 def : InstRW<[WriteImmZ], (instrs MOVZWi,MOVZXi,ANDWri,ANDXri)>;
126 def : InstRW<[WriteMov], (instrs COPY,ORRXrr,ADDXrr)>;
273 def : InstRW<[WriteST, WriteST], (instrs STPQi)>;
291 def : InstRW<[WriteI], (instrs ISB)>;
335 def : InstRW<[WriteVMov], (instrs ORRv16i8)>;
351 def : InstRW<[WriteLD], (instrs FMOVSWr,FMOVDXr,FMOVDXHighr)>;
432 def : InstRW<[CyWriteV4], (instrs FADDPv2i32p)>;
433 def : InstRW<[CyWriteV5], (instrs FADDPv2i64p)>;
440 def : InstRW<[CyWriteV4], (instrs FADDSrr,FADDv2f32,FADDv4f32,
444 def : InstRW<[CyWriteV5], (instrs FADDDrr,FADDv2f64,
[all …]
/external/minijail/
Dsyscall_filter_unittest_macros.h26 EXPECT_EQ((_block)->instrs->code, BPF_LD+BPF_W+BPF_ABS); \
32 EXPECT_EQ((_block)->instrs->code, BPF_LD+BPF_W+BPF_ABS); \
38 EXPECT_EQ((_block)->instrs->code, BPF_LD+BPF_W+BPF_ABS); \
66 EXPECT_JUMP_LBL(&(_block)->instrs[0]); \
67 EXPECT_LBL(&(_block)->instrs[1]); \
73 EXPECT_EQ_STMT((_block)->instrs, \
80 EXPECT_EQ_STMT((_block)->instrs, \
87 EXPECT_EQ_STMT((_block)->instrs, \
94 EXPECT_LBL(&(_block)->instrs[0]); \
95 EXPECT_EQ_STMT(&(_block)->instrs[1], \
Dsyscall_filter_unittest.cc509 EXPECT_LBL(curr_block->instrs); in TEST_F()
549 EXPECT_LBL(curr_block->instrs); in TEST_F()
589 EXPECT_LBL(curr_block->instrs); in TEST_F()
629 EXPECT_LBL(curr_block->instrs); in TEST_F()
672 EXPECT_LBL(curr_block->instrs); in TEST_F()
714 EXPECT_LBL(curr_block->instrs); in TEST_F()
754 EXPECT_LBL(curr_block->instrs); in TEST_F()
795 EXPECT_LBL(curr_block->instrs); in TEST_F()
801 EXPECT_EQ(curr_block->instrs[BPF_ARG_COMP_LEN - 1].k, in TEST_F()
837 EXPECT_LBL(curr_block->instrs); in TEST_F()
[all …]
Dsyscall_filter.c73 block->instrs = NULL; in new_filter_block()
79 void append_filter_block(struct filter_block *head, struct sock_filter *instrs, in append_filter_block() argument
88 if (head->instrs == NULL) { in append_filter_block()
101 new_last->instrs = instrs; in append_filter_block()
860 filter[_index++] = curr->instrs[i]; in flatten_block_list()
872 free(current->instrs); in free_block_list()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86ScheduleAtom.td122 def : InstRW<[AtomWriteIMul16Ld], (instrs MUL16m, IMUL16m)>;
128 def : InstRW<[AtomWriteIMul32], (instrs MUL32r, IMUL32r)>;
134 def : InstRW<[AtomWriteIMul64I], (instrs IMUL64rri8, IMUL64rri32,
169 def : InstRW<[WriteMove], (instrs COPY)>;
494 def : InstRW<[AtomWrite0_1], (instrs FXAM, LD_Frr,
512 def : InstRW<[AtomWrite1_1], (instrs FCOMPP)>;
520 def : InstRW<[AtomWrite1_5], (instrs MMX_CVTPI2PSirr, MMX_CVTPI2PSirm,
528 def : InstRW<[AtomWrite0_1_1], (instrs POP32r, POP64r,
542 def : InstRW<[AtomWrite0_1_5], (instrs MMX_CVTPS2PIirm, MMX_CVTTPS2PIirm)>;
550 def : InstRW<[AtomWrite01_1], (instrs FDECSTP, FFREE, FFREEP, FINCSTP, WAIT,
[all …]
DX86ScheduleZnver1.td211 def : InstRW<[WriteMove], (instrs COPY)>;
517 def : InstRW<[WriteMicrocoded], (instrs XLAT)>;
548 def : InstRW<[WriteMicrocoded], (instrs LAHF)>;
585 def : InstRW<[ZnWriteMul16], (instrs IMUL16r, MUL16r)>;
586 def : InstRW<[ZnWriteMul16], (instrs IMUL16rr, IMUL16rri, IMUL16rri8)>; // TODO: is this right?
587 def : InstRW<[ZnWriteMul16], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>; // TODO: this is definitely…
593 def : InstRW<[ZnWriteMul16Ld, ReadAfterLd], (instrs IMUL16m, MUL16m)>;
599 def : InstRW<[ZnWriteMul32], (instrs IMUL32r, MUL32r)>;
600 def : InstRW<[ZnWriteMul32], (instrs IMUL32rr, IMUL32rri, IMUL32rri8)>; // TODO: is this right?
601 def : InstRW<[ZnWriteMul32], (instrs IMUL32rm, IMUL32rmi, IMUL32rmi8)>; // TODO: this is definitely…
[all …]
DX86SchedHaswell.td601 def : InstRW<[HWWriteXLAT], (instrs XLAT)>;
668 def : InstRW<[HWWriteINTO], (instrs INTO)>;
684 def : InstRW<[HWWriteMOVS], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>;
700 def : InstRW<[HWWriteRDPMC], (instrs RDPMC)>;
747 def : InstRW<[HWWrite2P01], (instrs FCOMPP, UCOM_FPPr)>;
751 def : InstRW<[HWWrite3P01], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>;
757 def : InstRW<[HWWrite2P1], (instrs FXAM)>;
764 def : InstRW<[HWWriteFPREM], (instrs FPREM)>;
771 def : InstRW<[HWWriteFPREM1], (instrs FPREM1)>;
778 def : InstRW<[HWWriteFRNDINT], (instrs FRNDINT)>;
[all …]
DX86SchedBroadwell.td140 def : WriteRes<WriteBitTest,[BWPort06]>; // Bit Test instrs
173 def : InstRW<[WriteMove], (instrs COPY)>;
562 // Remaining instrs.
599 def: InstRW<[BWWriteResGroup5], (instrs FINCSTP, FNOP)>;
606 def: InstRW<[BWWriteResGroup6], (instrs CDQ, CQO)>;
649 def: InstRW<[BWWriteResGroup12], (instrs FDECSTP)>;
666 def: InstRW<[BWWriteResGroup14], (instrs LFENCE,
698 def: InstRW<[BWWriteResGroup18], (instrs SFENCE)>;
705 def: InstRW<[BWWriteResGroup20], (instrs CWD)>;
706 def: InstRW<[BWWriteResGroup20], (instrs JCXZ, JECXZ, JRCXZ)>;
[all …]
DX86SchedSkylakeClient.td564 // Remaining instrs.
601 def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>;
608 def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
634 def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE,
663 def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP)>;
682 def: InstRW<[SKLWriteResGroup17], (instrs LFENCE,
698 def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>;
705 def: InstRW<[SKLWriteResGroup23], (instrs CWD)>;
706 def: InstRW<[SKLWriteResGroup23], (instrs JCXZ, JECXZ, JRCXZ)>;
717 def: InstRW<[SKLWriteResGroup25], (instrs FNSTCW16m)>;
[all …]
DX86SchedSandyBridge.td546 // Remaining SNB instrs.
553 def: InstRW<[SBWriteResGroup1], (instrs COMP_FST0r,
563 def: InstRW<[SBWriteResGroup2], (instrs FDECSTP, FINCSTP, FFREE, FFREEP, FNOP,
565 def: InstRW<[SBWriteResGroup2], (instrs LOOP, LOOPE, LOOPNE)>; // FIXME: This seems wrong compared …
566 def: InstRW<[SBWriteResGroup2], (instrs RETQ)>;
573 def: InstRW<[SBWriteResGroup4], (instrs CDQ, CQO)>;
601 def: InstRW<[SBWriteResGroup11], (instrs SCASB,
621 def: InstRW<[SBWriteResGroup15], (instrs CWD,
629 def: InstRW<[SBWriteResGroup18], (instrs JCXZ, JECXZ, JRCXZ)>;
644 def: InstRW<[SBWriteResGroup21_16i], (instrs IMUL16rri, IMUL16rri8)>;
[all …]
DX86SchedSkylakeServer.td565 // Remaining instrs.
614 def: InstRW<[SKXWriteResGroup6], (instrs FINCSTP, FNOP)>;
621 def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
657 def: InstRW<[SKXWriteResGroup10], (instrs CBW, CWDE, CDQE,
687 def: InstRW<[SKXWriteResGroup14], (instrs FDECSTP)>;
706 def: InstRW<[SKXWriteResGroup17], (instrs LFENCE,
722 def: InstRW<[SKXWriteResGroup21], (instrs SFENCE)>;
729 def: InstRW<[SKXWriteResGroup23], (instrs CWD)>;
730 def: InstRW<[SKXWriteResGroup23], (instrs JCXZ, JECXZ, JRCXZ)>;
741 def: InstRW<[SKXWriteResGroup25], (instrs FNSTCW16m)>;
[all …]
/external/mesa3d/src/panfrost/bifrost/
Ddisassemble.c434 struct bifrost_alu_inst instrs[8] = {}; in dump_clause() local
473 instrs[idx + 1] = main_instr; in dump_clause()
474 instrs[idx].add_bits = bits(words[3], 0, 17) | ((tag & 0x7) << 17); in dump_clause()
475 instrs[idx].fma_bits |= bits(words[2], 19, 32) << 10; in dump_clause()
485 instrs[1] = main_instr; in dump_clause()
491 … instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17; in dump_clause()
492 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10; in dump_clause()
502 … instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17; in dump_clause()
503 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10; in dump_clause()
505 instrs[3] = main_instr; in dump_clause()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DP9InstrResources.td39 (instrs
91 (instrs
107 (instrs
124 (instrs
177 (instrs
206 (instrs
292 (instrs
402 (instrs
410 (instrs
455 (instrs
[all …]
/external/mesa3d/src/freedreno/afuc/
Ddisasm.c304 uint32_t *instrs = buf; in disasm() local
305 const int jmptbl_start = instrs[1] & 0xffff; in disasm()
323 afuc_instr *instr = (void *)&instrs[i]; in disasm()
353 afuc_instr *instr = (void *)&instrs[i]; in disasm()
393 printf("\t%04x: %08x ", i, instrs[i]); in disasm()
404 if (instrs[i] != nop) { in disasm()
405 printerr("[%08x]", instrs[i]); in disasm()
411 print_gpu_reg(instrs[i]); in disasm()
439 print_alu_name(opc, instrs[i]); in disasm()
505 printf("[%08x] ; ", instrs[i]); in disasm()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsScheduleP5600.td39 def : InstRW<[P5600WriteALU], (instrs AND, LUi, NOR, OR, SLTi, SLTiu, SUB,
64 def : InstRW<[P5600WriteJump], (instrs B, BAL, BAL_BR, BEQ, BEQL, BGEZ, BGEZAL,
75 def : InstRW<[P5600WriteJumpAndLink], (instrs JAL, JALR, JALRHBPseudo,
78 def : InstRW<[P5600WriteJumpAndLink], (instrs JALX)> {
84 def : InstRW<[P5600COP0], (instrs TLBINV, TLBINVF, TLBP, TLBR, TLBWI, TLBWR,
89 def : InstRW<[P5600COP2], (instrs MFC2, MTC2)> {
122 def : InstRW<[P5600WriteLoad], (instrs LB, LBu, LH, LHu, LW, LL, LWC2, LWC3,
127 def : InstRW<[P5600WriteLoadShifted], (instrs LWL, LWR, LWLE, LWRE)>;
130 def : InstRW<[P5600WriteStore], (instrs SB, SH, SW, SWC2, SWC3, SDC2, SDC3, SC,
134 def : InstRW<[P5600WriteCache], (instrs PREF, PREFE, CACHE, CACHEE, SYNC,
[all …]
/external/mesa3d/src/amd/compiler/
Daco_form_hard_clauses.cpp39 void emit_clause(Builder& bld, unsigned num_instrs, aco_ptr<Instruction> *instrs) in emit_clause() argument
44 for (; (start < num_instrs) && instrs[start]->definitions.empty(); start++) in emit_clause()
45 bld.insert(std::move(instrs[start])); in emit_clause()
48 for (; (end < num_instrs) && !instrs[end]->definitions.empty(); end++) in emit_clause()
56 bld.insert(std::move(instrs[i])); in emit_clause()
/external/mesa3d/src/freedreno/decode/
Dpgmdump.c522 uint8_t *instrs = NULL; in dump_shaders_a3xx() local
542 instrs = &vs_hdr[n]; in dump_shaders_a3xx()
552 instrs = ptr; in dump_shaders_a3xx()
576 dump_hex(instrs, instrs_size); in dump_shaders_a3xx()
584 instrs += ALIGN(instrs_size, 8) - instrs_size; in dump_shaders_a3xx()
587 instrs += 32; in dump_shaders_a3xx()
591 disasm_a3xx((uint32_t *)instrs, instrs_size / 4, level+1, stdout, gpu_id); in dump_shaders_a3xx()
592 dump_raw_shader((uint32_t *)instrs, instrs_size / 4, i, "vo3"); in dump_shaders_a3xx()
601 uint8_t *instrs = NULL; in dump_shaders_a3xx() local
620 instrs = &fs_hdr[n]; in dump_shaders_a3xx()
[all …]
/external/mesa3d/src/compiler/nir/
Dnir_opt_gcm.c75 struct exec_list instrs; member
260 exec_list_push_tail(&state->instrs, &instr->node); in gcm_pin_instructions()
612 exec_list_make_empty(&state.instrs); in opt_gcm_impl()
624 foreach_list_typed_safe(nir_instr, instr, node, &state.instrs) { in opt_gcm_impl()
633 foreach_list_typed(nir_instr, instr, node, &state.instrs) in opt_gcm_impl()
636 foreach_list_typed(nir_instr, instr, node, &state.instrs) in opt_gcm_impl()
639 while (!exec_list_is_empty(&state.instrs)) { in opt_gcm_impl()
641 state.instrs.tail_sentinel.prev, node); in opt_gcm_impl()

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