/external/clang/test/Index/skip-parsed-bodies/ |
D | compile_commands.json | 23 …]: kind: c++-instance-method | name: method_decl | {{.*}} | isRedecl: 0 | isDef: 0 | isContainer: 0 24 …]: kind: c++-instance-method | name: method_def1 | {{.*}} | isRedecl: 0 | isDef: 1 | isContainer: 1 26 …]: kind: c++-instance-method | name: method_def2 | {{.*}} | isRedecl: 0 | isDef: 0 | isContainer: 0 27 …]: kind: c++-instance-method | name: method_def2 | {{.*}} | isRedecl: 1 | isDef: 1 | isContainer: 1 31 // CHECK-NEXT: [indexDeclaration]: kind: function | name: foo1 | {{.*}} | isRedecl: 0 | isDef: 1 | … 39 …]: kind: c++-instance-method | name: method_decl | {{.*}} | isRedecl: 0 | isDef: 0 | isContainer: 0 40 …]: kind: c++-instance-method | name: method_def1 | {{.*}} | isRedecl: 0 | isDef: 1 | isContainer: … 41 …]: kind: c++-instance-method | name: method_def2 | {{.*}} | isRedecl: 0 | isDef: 0 | isContainer: 0 45 // CHECK-NEXT: [indexDeclaration]: kind: function | name: foo1 | {{.*}} | isRedecl: 0 | isDef: 1 | … 47 // CHECK-NEXT: [indexDeclaration]: kind: function | name: foo2 | {{.*}} | isRedecl: 0 | isDef: 1 | … [all …]
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/external/llvm/lib/CodeGen/ |
D | ImplicitNullChecks.cpp | 207 if (MO.isDef()) { in rememberInstruction() 266 assert((!MO.isDef() || RegDefs.count(MO.getReg())) && in isSafeToHoist() 268 return !MO.isDef() || RegDefs.find(MO.getReg())->second == MI; in isSafeToHoist() 282 if (MO.isDef()) in isSafeToHoist() 436 if (!MO.isReg() || !MO.getReg() || !MO.isDef()) in analyzeBlockForNullChecks() 542 if (!MO.isReg() || !MO.isDef()) in rewriteNullChecks() 552 if (!MO.isReg() || !MO.getReg() || !MO.isDef()) in rewriteNullChecks()
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D | LiveRangeCalc.cpp | 62 if (!MO.isDef() && !MO.readsReg()) in calculate() 93 if (MO.isDef()) in calculate() 100 if (MO.isDef()) in calculate() 107 if (MO.isDef() && !LI.hasSubRanges()) in calculate() 188 assert(!MO.isDef() && "Cannot handle PHI def of partial register."); in extendToUses() 196 if (MO.isDef()) in extendToUses()
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D | MachineInstrBundle.cpp | 141 if (MO.isDef()) { in finalizeBundle() 280 if (MO.isDef()) in analyzeVirtReg() 285 if (MO.isDef()) in analyzeVirtReg() 327 } else if (MO.isDef()) { in analyzePhysReg()
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D | MachineInstr.cpp | 177 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, in ChangeToRegister() argument 195 IsDef = isDef; in ChangeToRegister() 225 return getReg() == Other.getReg() && isDef() == Other.isDef() && in isIdenticalTo() 268 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef()); in hash_value() 319 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || in print() 323 if (isDef()) { in print() 1004 if (MO.isDef()) { in isIdenticalTo() 1058 if (!MO.isReg() || !MO.isDef()) in eraseFromParentAndMarkDBGValuesForRemoval() 1349 if (!MO.isReg() || !MO.isDef()) in findRegisterDefOperandIdx() 1402 assert(DefMO.isDef() && "DefIdx must be a def operand"); in tieOperands() [all …]
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D | MachineLICM.cpp | 386 if (!MO.isDef()) { in ProcessMI() 505 if (!MO.isReg() || MO.isDef() || !MO.getReg()) in HoistRegionPostRA() 531 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue; in AddToLiveIns() 719 if (!MO.isDef() || !MO.isReg() || !MO.getReg()) in SinkIntoLoop() 814 if (MO.isDef()) in calcRegisterCost() 937 if (!MO.isReg() || !MO.isDef()) in HasLoopPHIUse() 1006 if (!DefMO.isReg() || !DefMO.isDef()) in IsCheapInstruction() 1101 if (MO.isDef() && HasHighOperandLatency(MI, i, Reg)) { in IsProfitableToHoist() 1254 if (MO.isReg() && MO.isDef() && in EliminateCSE() 1346 if (MO.isReg() && MO.isDef() && !MO.isDead()) in Hoist()
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D | RenameIndependentSubregs.cpp | 180 if (!MO.isDef() && !MO.readsReg()) in findComponents() 190 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber()) in findComponents() 219 if (!MO.isDef() && !MO.readsReg()) in rewriteOperands() 334 if (!MO.isDef()) in computeMainRangesFixFlags()
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D | DeadMachineInstructionElim.cpp | 79 if (MO.isReg() && MO.isDef()) { in isDead() 145 if (MO.isReg() && MO.isDef()) { in runOnMachineFunction()
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D | VirtRegMap.cpp | 411 if (MO.readsReg() && (MO.isDef() || MO.isKill())) in rewrite() 414 if (MO.isDef()) { in rewrite() 429 assert(MO.isDef()); in rewrite() 437 if (MO.isDef()) in rewrite()
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D | CriticalAntiDepBreaker.cpp | 261 if (!MO.isDef()) continue; in ScanInstruction() 341 if (RefOper->isDef() && RefOper->isEarlyClobber()) in isNewRegClobberedByRefs() 352 if (!CheckOper.isReg() || !CheckOper.isDef() || in isNewRegClobberedByRefs() 358 if (RefOper->isDef()) in isNewRegClobberedByRefs() 607 if (MO.isDef() && Reg != AntiDepReg) in BreakAntiDependencies()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
D | ImplicitNullChecks.cpp | 286 if (TRI->regsOverlap(RegA, RegB) && (MOA.isDef() || MOB.isDef())) in canReorder() 439 assert(!(DependenceMO.isDef() && in canHoistInst() 598 return MO.isReg() && MO.getReg() && MO.isDef() && in analyzeBlockForNullChecks() 645 assert(MO.isDef() && "Expected def or use"); in insertFaultingInstr() 687 if (!MO.isReg() || !MO.isDef()) in rewriteNullChecks() 697 if (!MO.isReg() || !MO.getReg() || !MO.isDef()) in rewriteNullChecks()
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D | MachineOperand.cpp | 90 if (isDef()) in substPhysReg() 125 if (isDef()) in isRenamable() 219 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, in ChangeToRegister() argument 232 assert(!(isDead && !isDef) && "Dead flag on non-def"); in ChangeToRegister() 233 assert(!(isKill && isDef) && "Kill flag on def"); in ChangeToRegister() 237 IsDef = isDef; in ChangeToRegister() 267 return getReg() == Other.getReg() && isDef() == Other.isDef() && in isIdenticalTo() 331 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef()); in hash_value() 731 OS << (isDef() ? "implicit-def " : "implicit "); in print() 732 else if (PrintDef && isDef()) in print() [all …]
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D | LiveRangeCalc.cpp | 84 if (!MO.isDef() && !MO.readsReg()) in calculate() 100 if (MO.isDef()) in calculate() 107 if (MO.isDef() && !LI.hasSubRanges()) in calculate() 174 if (!MO.readsReg() || (IsSubRange && MO.isDef())) in extendToUses() 180 if (MO.isDef()) in extendToUses() 192 assert(!MO.isDef() && "Cannot handle PHI def of partial register."); in extendToUses() 200 if (MO.isDef()) in extendToUses()
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D | RenameIndependentSubregs.cpp | 180 if (!MO.isDef() && !MO.readsReg()) in findComponents() 190 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber()) in findComponents() 219 if (!MO.isDef() && !MO.readsReg()) in rewriteOperands() 224 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber()) in rewriteOperands() 346 if (!MO.isDef()) in computeMainRangesFixFlags()
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D | MachineInstrBundle.cpp | 143 if (MO.isDef()) { in finalizeBundle() 282 if (MO.isDef()) in analyzeVirtReg() 287 if (MO.isDef()) in analyzeVirtReg() 329 } else if (MO.isDef()) { in analyzePhysReg()
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D | LiveRangeEdit.cpp | 193 if (MO.isDef()) { in foldAsLoad() 291 if (VRM && MI->getOperand(0).isReg() && MI->getOperand(0).isDef() && in eliminateDeadDef() 315 else if (MOI->isDef()) in eliminateDeadDef() 325 if ((MI->readsVirtualRegister(Reg) && (MI->isCopy() || MOI->isDef())) || in eliminateDeadDef() 330 if (MOI->isDef()) { in eliminateDeadDef()
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D | RegisterScavenging.cpp | 148 assert(MO.isDef()); in determineKillsAndDefs() 244 assert(MO.isDef()); in forward() 334 if (MO.isDef()) in findSurvivorReg() 629 if (MO.isDef()) { in scavengeVReg() 721 assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses"); in scavengeFrameVirtualRegsInBlock() 725 if (MO.isDef()) { in scavengeFrameVirtualRegsInBlock() 736 assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses"); in scavengeFrameVirtualRegsInBlock()
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D | MachineLICM.cpp | 434 if (!MO.isDef()) { in ProcessMI() 553 if (!MO.isReg() || MO.isDef() || !MO.getReg()) in HoistRegionPostRA() 579 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue; in AddToLiveIns() 769 if (!MO.isDef() || !MO.isReg() || !MO.getReg()) in SinkIntoLoop() 864 if (MO.isDef()) in calcRegisterCost() 1061 if (!MO.isReg() || !MO.isDef()) in HasLoopPHIUse() 1131 if (!DefMO.isReg() || !DefMO.isDef()) in IsCheapInstruction() 1230 if (MO.isDef() && HasHighOperandLatency(MI, i, Reg)) { in IsProfitableToHoist() 1384 if (MO.isReg() && MO.isDef() && in EliminateCSE() 1486 if (MO.isReg() && MO.isDef() && !MO.isDead()) in Hoist()
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D | DeadMachineInstructionElim.cpp | 78 if (MO.isReg() && MO.isDef()) { in isDead() 141 if (MO.isReg() && MO.isDef()) { in runOnMachineFunction()
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D | LiveRegUnits.cpp | 49 if (!O->isDef() || O->isDebug()) in stepBackward() 77 if (!O->isDef() && !O->readsReg()) in accumulate()
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D | MachineInstr.cpp | 449 if (MO.isDef()) { in isIdenticalTo() 507 if (!MO.isReg() || !MO.isDef()) in eraseFromParentAndMarkDBGValuesForRemoval() 548 if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) in getNumExplicitDefs() 822 if (!MO.isReg() || !MO.isDef()) in findRegisterDefOperandIdx() 875 assert(DefMO.isDef() && "DefIdx must be a def operand"); in tieOperands() 1223 if (!Operand.isReg() || Operand.isDef()) in hasComplexRegisterTies() 1302 if (MO.isReg() && MO.isTied() && !MO.isDef()) in print() 1312 if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) in print() 1650 if (!MO.isReg() || !MO.isDef()) in addRegisterDead() 1694 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg) in clearRegisterDeads() [all …]
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/external/llvm/include/llvm/CodeGen/ |
D | MachineOperand.h | 282 bool isDef() const { in isDef() function 580 void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false, 606 static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false, 613 assert(!(isDead && !isDef) && "Dead flag on non-def"); 614 assert(!(isKill && isDef) && "Kill flag on def"); 616 Op.IsDef = isDef;
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
D | MachineOperand.h | 364 bool isDef() const { in isDef() function 730 void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false, 756 static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false, 763 assert(!(isDead && !isDef) && "Dead flag on non-def"); 764 assert(!(isKill && isDef) && "Kill flag on def"); 766 Op.IsDef = isDef;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
D | X86FixupBWInsts.cpp | 250 assert((MO.isDef() || MO.isUse()) && "Expected Def or Use only!"); in getSuperRegDestIfDead() 252 if (MO.isDef() && TRI->isSuperRegisterEq(OrigDestReg, MO.getReg())) in getSuperRegDestIfDead() 326 if (Op.getReg() != (Op.isDef() ? NewDestReg : NewSrcReg)) in tryReplaceCopy()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64DeadRegisterDefinitionsPass.cpp | 72 if (MO.isReg() && MO.isDef()) in implicitlyDefinesOverlappingReg() 104 if (MO.isReg() && MO.isDead() && MO.isDef()) { in processMachineBasicBlock()
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