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Searched refs:kQRegSize (Results 1 – 14 of 14) sorted by relevance

/external/vixl/benchmarks/aarch64/
Dbench-utils.cc128 __ Claim((4 * kQRegSize) + (16 * GetRandomBits(3))); in GeneratePrologue()
386 VRegister vt(16 + static_cast<unsigned>(GetRandomBits(4)), kQRegSize); in GenerateNEONSequence()
387 VRegister vt2((vt.GetCode() + 1) % kNumberOfVRegisters, kQRegSize); in GenerateNEONSequence()
388 VRegister vt3((vt.GetCode() + 2) % kNumberOfVRegisters, kQRegSize); in GenerateNEONSequence()
389 VRegister vt4((vt.GetCode() + 3) % kNumberOfVRegisters, kQRegSize); in GenerateNEONSequence()
Dbench-utils.h234 unsigned size_in_bits = vixl::aarch64::kQRegSize);
/external/vixl/src/aarch64/
Doperands-aarch64.h151 (size_ == kQRegSize)) && in IsValidVRegister()
368 VRegister V16B() const { return VRegister(code_, kQRegSize, 16); } in V16B()
371 VRegister V8H() const { return VRegister(code_, kQRegSize, 8); } in V8H()
373 VRegister V4S() const { return VRegister(code_, kQRegSize, 4); } in V4S()
374 VRegister V2D() const { return VRegister(code_, kQRegSize, 2); } in V2D()
468 const VRegister q##N(N, kQRegSize); \
469 const VRegister v##N(N, kQRegSize);
Dinstructions-aarch64.h75 const unsigned kQRegSize = 128; variable
77 const unsigned kQRegSizeInBytes = kQRegSize / 8;
Dinstructions-aarch64.cc561 return kQRegSize; in RegisterSizeInBitsFromFormat()
Ddisasm-aarch64.cc5295 reg_size = kQRegSize; in SubstituteRegisterField()
/external/vixl/examples/aarch64/
Dneon-matrix-multiply.cc50 VRegister v_out = VRegister(out_column, kQRegSize, 4); in GenerateMultiplyColumn()
/external/v8/src/execution/arm64/
Dsimulator-arm64.h372 using SimVRegister = SimRegisterBase<kQRegSize>; // v0-v31
515 for (unsigned i = size; i < kQRegSize; i++) { in ClearForWrite()
636 Saturation saturated_[kQRegSize];
639 bool round_[kQRegSize];
991 uint8_t val[kQRegSize];
999 (sizeof(T) == kQRegSize), in vreg()
1061 (sizeof(value) == kQRegSize),
1113 (sizeof(value) == kDRegSize) || (sizeof(value) == kQRegSize)); in set_vreg_no_log()
1378 void PrintVRegisterRawHelper(unsigned code, int bytes = kQRegSize,
Dsimulator-arm64.cc1006 case kQRegSize: in GetPrintRegisterFormatForSize()
1018 case kQRegSize: in GetPrintRegisterFormatForSize()
1220 int byte = kQRegSize - 1; in PrintVRegisterRawHelper()
1259 DCHECK_LE(msb, static_cast<unsigned>(kQRegSize)); in PrintVRegisterFPHelper()
1273 if (msb < (kQRegSize - 1)) { in PrintVRegisterFPHelper()
2023 DCHECK_EQ(access_size, static_cast<unsigned>(kQRegSize)); in LoadStorePairHelper()
2059 DCHECK_EQ(access_size, static_cast<unsigned>(kQRegSize)); in LoadStorePairHelper()
/external/v8/src/codegen/arm64/
Dconstants-arm64.h68 const int kQRegSize = kQRegSizeInBits >> 3; variable
Dassembler-arm64.cc2538 DCHECK_LT(lane, kQRegSize / lane_size); in LoadStoreStructSingle()
/external/vixl/test/aarch64/
Dtest-simulator-aarch64.cc1691 VRegister vdstr = VRegister(0, kQRegSize); in Test1OpAcrossNEON_Helper()
2183 VIXL_ASSERT((vm_bits * vm_subvector_count) <= kQRegSize); in TestByElementNEON_Helper()
Dtest-assembler-aarch64.cc13248 VRegister temp = temps.AcquireVRegisterOfSize(kQRegSize); in TEST()
/external/v8/src/diagnostics/arm64/
Ddisasm-arm64.cc3732 imm *= (instr->NEONQ() == 0) ? kDRegSize : kQRegSize; in SubstituteRegisterField()