| /external/u-boot/arch/arm/mach-mvebu/serdes/a38x/ |
| D | high_speed_env_spec-38x.c | 81 int hws_is_serdes_active(u8 lane_num) in hws_is_serdes_active() argument
86 if (lane_num > 6) in hws_is_serdes_active()
90 if (sys_env_device_id_get() == MV_6810 && lane_num == 4) { in hws_is_serdes_active()
100 if (sys_env_device_id_get() == MV_6810 && lane_num == 5) in hws_is_serdes_active()
103 if (lane_num >= hws_serdes_get_max_lane()) in hws_is_serdes_active()
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| D | high_speed_env_spec.c | 1365 u32 lane_num; in print_topology_details() local
1371 for (lane_num = 0; lane_num < count; lane_num++) { in print_topology_details()
1372 if (serdes_map[lane_num].serdes_type == DEFAULT_SERDES) in print_topology_details()
1375 DEBUG_INIT_D(hws_get_physical_serdes_num(lane_num), 1); in print_topology_details()
1377 DEBUG_INIT_D(serdes_map[lane_num].serdes_speed, 2); in print_topology_details()
1380 serdes_type_to_string[serdes_map[lane_num]. in print_topology_details()
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| D | high_speed_env_spec.h | 248 int hws_is_serdes_active(u8 lane_num);
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| /external/u-boot/drivers/video/exynos/ |
| D | exynos_dp.c | 416 unsigned char lane_num, unsigned char *sw, unsigned char *em) in exynos_dp_read_dpcd_adj_req() argument
424 dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2); in exynos_dp_read_dpcd_adj_req()
432 *sw = ((buf >> shift_val[lane_num]) & 0x03); in exynos_dp_read_dpcd_adj_req()
433 *em = ((buf >> shift_val[lane_num]) & 0x0c) >> 2; in exynos_dp_read_dpcd_adj_req()
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| /external/tensorflow/tensorflow/lite/kernels/internal/optimized/ |
| D | depthwiseconv_uint8_3x3_filter.h | 42 #define vst1_lane_8x4(dst, reg, lane_num) \ argument
45 lane_num)
46 #define vst1q_lane_8x4(dst, reg, lane_num) \ argument
48 vst1q_lane_u32(reinterpret_cast<uint32_t*>(dst), reg, lane_num)
53 #define vld1q_lane_s8x8(src, reg, lane_num) \ argument
55 vreinterpretq_s64_s8(reg), lane_num))
56 #define vld1_lane_8x4(src, reg, lane_num) \ argument
58 vreinterpret_s32_s8(reg), lane_num))
59 #define vld1q_lane_8x4(src, reg, lane_num) \ argument
60 vld1q_lane_s32(reinterpret_cast<const int32*>(src), reg, lane_num)
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| D | depthwiseconv_uint8_transitional.h | 63 #define vst1_lane_8x4(dst, reg, lane_num) \ argument
65 vst1_lane_u32(reinterpret_cast<uint32_t*>(dst), reg, lane_num)
66 #define vst1q_lane_8x4(dst, reg, lane_num) \ argument
68 vst1q_lane_u32(reinterpret_cast<uint32_t*>(dst), reg, lane_num)
73 #define vld1q_lane_s8x8(src, reg, lane_num) \ argument
74 vld1q_lane_u64(reinterpret_cast<const uint64_t*>(src), reg, lane_num)
75 #define vld1_lane_8x4(src, reg, lane_num) \ argument
76 vld1_lane_s32(reinterpret_cast<const int32*>(src), reg, lane_num)
77 #define vld1q_lane_8x4(src, reg, lane_num) \ argument
78 vld1q_lane_s32(reinterpret_cast<const int32*>(src), reg, lane_num)
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| /external/v8/src/execution/s390/ |
| D | simulator-s390.cc | 3748 int8_t lane_num = get_simd_register_by_lane<int8_t>(r4, i); in EVALUATE() local
3750 lane_num = (lane_num << 3) >> 3; in EVALUATE()
3752 if (lane_num >= kSimd128Size) { in EVALUATE()
3753 lane_num = lane_num - kSimd128Size; in EVALUATE()
3756 int8_t result = get_simd_register_by_lane<int8_t>(reg, lane_num); in EVALUATE()
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