| /external/gemmlowp/meta/generators/ |
| D | zip_Nx8_neon.py | 40 lanes = []
44 lanes.append(ZipLane(input_address, registers.DoubleRegister(),
48 lanes.append(ZipLane(address_register, registers.DoubleRegister(),
52 return lanes
64 def GenerateClearAggregators(emitter, lanes): argument
65 for lane in lanes:
69 def GenerateLoadAggregateStore(emitter, lanes, output_address, alignment): argument
74 for lane in lanes:
80 for lane in lanes:
88 def GenerateLeftoverLoadAggregateStore(emitter, leftovers, lanes, argument
[all …]
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| D | qnt_Nx8_neon.py | 26 def BuildName(lanes, leftovers, aligned): argument
27 name = 'qnt_%dx8' % lanes
35 def LoadAndDuplicateOffsets(emitter, registers, lanes, offsets): argument
36 if lanes == 1 or lanes == 2 or lanes == 3:
38 for unused_i in range(0, lanes):
46 raise ConfigurationError('Unsupported number of lanes: %d' % lanes)
55 lanes = []
60 lanes.append(QntLane(source,
68 lanes.append(QntLane(input_register,
77 return lanes
[all …]
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| D | mul_Nx8_Mx8_neon.py | 22 self.lanes = []
25 self.lanes.append(lane)
28 for i in range(0, len(self.lanes)):
29 registers.FreeRegister(self.lanes[i])
30 self.lanes[i] = None
34 lanes = MulLanes(address)
36 lanes.AddLane(registers.DoubleRegister())
37 return lanes
41 lanes = MulLanes(address)
42 lanes.AddLane(registers.Low(quad_register))
[all …]
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| /external/gemmlowp/meta/ |
| D | test_streams_correctness.cc | 105 template <int lanes, int leftover>
116 prepare_row_major_data(lanes, all_elements, stride, in); in test_2()
117 Stream<std::uint8_t, lanes, 8, leftover, RowMajorWithSum>::Pack(in, params, in test_2()
119 if (check(out, lanes, all_elements)) { in test_2()
124 std::cout << "Row: " << lanes << "x8x" << leftover << " : " in test_2()
131 for (int stride = lanes; stride < lanes + 4; ++stride) { in test_2()
138 prepare_column_major_data(lanes, all_elements, stride, in); in test_2()
139 Stream<std::uint8_t, lanes, 8, leftover, ColumnMajorWithSum>::Pack(in, params, in test_2()
141 if (check(out, lanes, all_elements)) { in test_2()
146 std::cout << "Column: " << lanes << "x8x" << leftover << " : " in test_2()
[all …]
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| /external/u-boot/arch/arm/dts/ |
| D | tegra210-p2371-2180.dts | 42 nvidia,lanes = "otg-1", "otg-2";
48 nvidia,lanes = "pcie-5", "pcie-6";
54 nvidia,lanes = "pcie-0";
60 nvidia,lanes = "pcie-1", "pcie-2",
67 nvidia,lanes = "sata-0";
|
| D | tegra186-p2771-0000-000.dts | 19 nvidia,num-lanes = <2>;
24 nvidia,num-lanes = <1>;
29 nvidia,num-lanes = <1>;
|
| D | tegra186-p2771-0000-500.dts | 19 nvidia,num-lanes = <4>;
24 nvidia,num-lanes = <0>;
29 nvidia,num-lanes = <1>;
|
| D | imx6dl-sabresd.dts | 16 clock-lanes = <0>;
17 data-lanes = <1 2>;
|
| D | imx6q-sabresd.dts | 21 clock-lanes = <0>;
22 data-lanes = <1 2>;
|
| /external/u-boot/arch/arm/cpu/armv8/fsl-layerscape/ |
| D | ls1012a_serdes.c | 12 u8 lanes[SRDS_MAX_LANES]; member
42 return ptr->lanes[lane]; in serdes_get_prtcl()
68 if (ptr->lanes[i] != NONE) in is_serdes_prtcl_valid()
|
| D | ls1043a_serdes.c | 12 u8 lanes[SRDS_MAX_LANES]; member
54 return ptr->lanes[lane]; in serdes_get_prtcl()
80 if (ptr->lanes[i] != NONE) in is_serdes_prtcl_valid()
|
| D | ls1046a_serdes.c | 13 u8 lanes[SRDS_MAX_LANES]; member
69 return ptr->lanes[lane]; in serdes_get_prtcl()
95 if (ptr->lanes[i] != NONE) in is_serdes_prtcl_valid()
|
| D | ls1028a_serdes.c | 11 u8 lanes[SRDS_MAX_LANES]; member
55 return ptr->lanes[lane]; in serdes_get_prtcl()
81 if (ptr->lanes[i] != NONE) in is_serdes_prtcl_valid()
|
| D | ls1088a_serdes.c | 11 u8 lanes[SRDS_MAX_LANES]; member
94 return ptr->lanes[lane]; in serdes_get_prtcl()
120 if (ptr->lanes[i] != NONE) in is_serdes_prtcl_valid()
|
| /external/u-boot/arch/powerpc/cpu/mpc85xx/ |
| D | fsl_corenet_serdes.c | 65 } lanes[SRDS_MAX_LANES] = { variable
99 return lanes[lane].idx; in serdes_get_lane_idx()
104 return lanes[lane].bank; in serdes_get_bank_by_lane()
112 int bank = lanes[lane].bank; in serdes_lane_enabled()
113 int word = lanes[lane].lpd / 32; in serdes_lane_enabled()
114 int bit = lanes[lane].lpd % 32; in serdes_lane_enabled()
671 if (lanes[lane].bank == bank) in fsl_serdes_init()
673 idx = lanes[lane].idx; in fsl_serdes_init()
|
| D | c29x_serdes.c | 18 u8 lanes[SRDS1_MAX_LANES]; member
64 enum srds_prtcl lane_prtcl = ptr->lanes[lane]; in fsl_serdes_init()
|
| /external/u-boot/drivers/video/ |
| D | anx9804.h | 19 void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp);
21 static inline void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, in anx9804_init() argument
|
| /external/u-boot/doc/device-tree-bindings/net/ |
| D | ti,dp83867.txt | 11 - enet-phy-lane-swap - Indicates that PHY will swap the TX/RX lanes to
12 compensate for the board being designed with the lanes swapped.
14 TX/RX lanes.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | detect-dead-lanes.mir | 1 # RUN: llc -march=amdgcn -run-pass detect-dead-lanes -o - %s | FileCheck %s
42 # Check defined lanes transfer; Includes checking for some special cases like
122 # Check used lanes transfer; Includes checking for some special cases like
203 # Check that copies to physregs use all lanes, copies from physregs define all
204 # lanes. So we should not get a dead/undef flag here.
296 ; let's swiffle some lanes around for fun...
308 # for the used lanes. The example reads sub3 lane at the end, however with each
349 ; rotate lanes, but skip sub2 lane...
359 # Similar to loop1 test, but check for fixpoint of defined lanes.
392 ; rotate subreg lanes, skipping sub1
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | detect-dead-lanes.mir | 1 # RUN: llc -march=amdgcn -run-pass detect-dead-lanes -o - %s | FileCheck %s
53 # Check defined lanes transfer; Includes checking for some special cases like
134 # Check used lanes transfer; Includes checking for some special cases like
216 # Check that copies to physregs use all lanes, copies from physregs define all
217 # lanes. So we should not get a dead/undef flag here.
315 ; let's swiffle some lanes around for fun...
327 # for the used lanes. The example reads sub3 lane at the end, however with each
371 ; rotate lanes, but skip sub2 lane...
381 # Similar to loop1 test, but check for fixpoint of defined lanes.
417 ; rotate subreg lanes, skipping sub1
|
| /external/skqp/src/compute/hs/gen/ |
| D | target_opencl.c | 305 m->warps * config->warp.lanes, in hsg_target_opencl()
334 m->warps * config->warp.lanes, in hsg_target_opencl()
500 ops->b * config->warp.lanes, in hsg_target_opencl()
508 ops->b * config->warp.lanes, in hsg_target_opencl()
518 ops->b * config->warp.lanes); in hsg_target_opencl()
526 ops->b * config->warp.lanes); in hsg_target_opencl()
|
| D | target_cuda.c | 336 m->warps * config->warp.lanes, in hsg_target_cuda()
373 m->warps * config->warp.lanes, in hsg_target_cuda()
569 ops->b * config->warp.lanes, in hsg_target_cuda()
577 ops->b * config->warp.lanes, in hsg_target_cuda()
587 ops->b * config->warp.lanes); in hsg_target_cuda()
595 ops->b * config->warp.lanes); in hsg_target_cuda()
|
| D | target_glsl.c | 324 m->warps * config->warp.lanes, in hsg_target_glsl()
369 m->warps * config->warp.lanes, in hsg_target_glsl()
588 ops->b * config->warp.lanes, in hsg_target_glsl()
596 ops->b * config->warp.lanes, in hsg_target_glsl()
606 ops->b * config->warp.lanes); in hsg_target_glsl()
614 ops->b * config->warp.lanes); in hsg_target_glsl()
|
| /external/u-boot/drivers/pci/ |
| D | pci_tegra.c | 380 static int tegra_pcie_get_xbar_config(ofnode node, u32 lanes, in tegra_pcie_get_xbar_config() argument
385 switch (lanes) { in tegra_pcie_get_xbar_config()
398 switch (lanes) { in tegra_pcie_get_xbar_config()
417 switch (lanes) { in tegra_pcie_get_xbar_config()
430 switch (lanes) { in tegra_pcie_get_xbar_config()
454 static int tegra_pcie_parse_port_info(ofnode node, uint *index, uint *lanes) in tegra_pcie_parse_port_info() argument
465 *lanes = err; in tegra_pcie_parse_port_info()
487 u32 lanes = 0; in tegra_pcie_parse_dt() local
535 lanes |= num_lanes << (index << 3); in tegra_pcie_parse_dt()
558 err = tegra_pcie_get_xbar_config(dev_ofnode(dev), lanes, id, in tegra_pcie_parse_dt()
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| /external/u-boot/drivers/video/bridge/ |
| D | anx6345.c | 270 u8 chipid, colordepth, lanes, data_rate, c; in anx6345_enable() local
357 if (anx6345_read_dpcd(dev, DP_MAX_LANE_COUNT, &lanes)) { in anx6345_enable()
361 lanes &= DP_MAX_LANE_COUNT_MASK; in anx6345_enable()
362 debug("%s: lanes: %d\n", __func__, (int)lanes); in anx6345_enable()
366 anx6345_write_r0(dev, ANX9804_LANE_COUNT_SET_REG, lanes); in anx6345_enable()
|