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Searched refs:ld3r (Results 1 – 25 of 54) sorted by relevance

123

/external/capstone/suite/MC/AArch64/
Dneon-simd-ldst-one-elem.s.cs18 0x00,0xe0,0x40,0x4d = ld3r {v0.16b, v1.16b, v2.16b}, [x0]
19 0xef,0xe5,0x40,0x4d = ld3r {v15.8h, v16.8h, v17.8h}, [x15]
20 0xff,0xeb,0x40,0x4d = ld3r {v31.4s, v0.4s, v1.4s}, [sp]
21 0x00,0xec,0x40,0x4d = ld3r {v0.2d, v1.2d, v2.2d}, [x0]
22 0x00,0xe0,0x40,0x0d = ld3r {v0.8b, v1.8b, v2.8b}, [x0]
23 0xef,0xe5,0x40,0x0d = ld3r {v15.4h, v16.4h, v17.4h}, [x15]
24 0xff,0xeb,0x40,0x0d = ld3r {v31.2s, v0.2s, v1.2s}, [sp]
25 0xff,0xef,0x40,0x0d = ld3r {v31.1d, v0.1d, v1.1d}, [sp]
82 0x00,0xe0,0xc9,0x4d = ld3r {v0.16b, v1.16b, v2.16b}, [x0], x9
83 0xef,0xe5,0xc6,0x4d = ld3r {v15.8h, v16.8h, v17.8h}, [x15], x6
[all …]
/external/llvm/test/MC/AArch64/
Dneon-simd-ldst-one-elem.s46 ld3r { v0.16b, v1.16b, v2.16b }, [x0]
47 ld3r { v15.8h, v16.8h, v17.8h }, [x15]
48 ld3r { v31.4s, v0.4s, v1.4s }, [sp]
49 ld3r { v0.2d, v1.2d, v2.2d }, [x0]
50 ld3r { v0.8b, v1.8b, v2.8b }, [x0]
51 ld3r { v15.4h, v16.4h, v17.4h }, [x15]
52 ld3r { v31.2s, v0.2s, v1.2s }, [sp]
53 ld3r { v31.1d, v0.1d, v1.1d }, [sp]
207 ld3r { v0.16b, v1.16b, v2.16b }, [x0], x9
208 ld3r { v15.8h, v16.8h, v17.8h }, [x15], x6
[all …]
Darm64-simd-ldst.s958 ld3r: label
959 ld3r.8b {v4, v5, v6}, [x2]
960 ld3r.8b {v4, v5, v6}, [x2], x3
961 ld3r.16b {v4, v5, v6}, [x2]
962 ld3r.16b {v4, v5, v6}, [x2], x3
963 ld3r.4h {v4, v5, v6}, [x2]
964 ld3r.4h {v4, v5, v6}, [x2], x3
965 ld3r.8h {v4, v5, v6}, [x2]
966 ld3r.8h {v4, v5, v6}, [x2], x3
967 ld3r.2s {v4, v5, v6}, [x2]
[all …]
Dneon-diagnostics.s4195 ld3r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
4254 ld3r {v15.4h, v16.4h, v17.4h}, [x15], #1
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-simd-ldst-one-elem.s46 ld3r { v0.16b, v1.16b, v2.16b }, [x0]
47 ld3r { v15.8h, v16.8h, v17.8h }, [x15]
48 ld3r { v31.4s, v0.4s, v1.4s }, [sp]
49 ld3r { v0.2d, v1.2d, v2.2d }, [x0]
50 ld3r { v0.8b, v1.8b, v2.8b }, [x0]
51 ld3r { v15.4h, v16.4h, v17.4h }, [x15]
52 ld3r { v31.2s, v0.2s, v1.2s }, [sp]
53 ld3r { v31.1d, v0.1d, v1.1d }, [sp]
207 ld3r { v0.16b, v1.16b, v2.16b }, [x0], x9
208 ld3r { v15.8h, v16.8h, v17.8h }, [x15], x6
[all …]
Darm64-simd-ldst.s958 ld3r: label
959 ld3r.8b {v4, v5, v6}, [x2]
960 ld3r.8b {v4, v5, v6}, [x2], x3
961 ld3r.16b {v4, v5, v6}, [x2]
962 ld3r.16b {v4, v5, v6}, [x2], x3
963 ld3r.4h {v4, v5, v6}, [x2]
964 ld3r.4h {v4, v5, v6}, [x2], x3
965 ld3r.8h {v4, v5, v6}, [x2]
966 ld3r.8h {v4, v5, v6}, [x2], x3
967 ld3r.2s {v4, v5, v6}, [x2]
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-ld1.ll566 ; CHECK: ld3r.8b { v0, v1, v2 }, [x0]
568 %tmp2 = call %struct.__neon_int8x8x3_t @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8* %A)
582 declare %struct.__neon_int8x8x3_t @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8*) nounwind readonly
597 ; CHECK: ld3r.16b { v0, v1, v2 }, [x0]
599 %tmp2 = call %struct.__neon_int8x16x3_t @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8* %A)
613 declare %struct.__neon_int8x16x3_t @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8*) nounwind readonly
628 ; CHECK: ld3r.4h { v0, v1, v2 }, [x0]
630 %tmp2 = call %struct.__neon_int16x4x3_t @llvm.aarch64.neon.ld3r.v4i16.p0i16(i16* %A)
644 declare %struct.__neon_int16x4x3_t @llvm.aarch64.neon.ld3r.v4i16.p0i16(i16*) nounwind readonly
659 ; CHECK: ld3r.8h { v0, v1, v2 }, [x0]
[all …]
Dfp16-vector-load-store.ll225 declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3r.v4f16.p0f16(half*)
228 declare { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3r.v8f16.p0f16(half*)
243 ; CHECK: ld3r { v0.4h, v1.4h, v2.4h }, [x0]
245 …%0 = tail call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3r.v4f16.p0f16(half* %a)
270 ; CHECK: ld3r { v0.8h, v1.8h, v2.8h }, [x0]
272 …%0 = tail call { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3r.v8f16.p0f16(half* %a)
Darm64-indexed-vector-ldst.ll2376 ;CHECK: ld3r.16b { v0, v1, v2 }, [x0], #3
2377 %ld3 = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8* %A)
2385 ;CHECK: ld3r.16b { v0, v1, v2 }, [x0], x{{[0-9]+}}
2386 %ld3 = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8* %A)
2392 declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8*) nounwind readon…
2397 ;CHECK: ld3r.8b { v0, v1, v2 }, [x0], #3
2398 %ld3 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8* %A)
2406 ;CHECK: ld3r.8b { v0, v1, v2 }, [x0], x{{[0-9]+}}
2407 %ld3 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8* %A)
2413 declare { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8*) nounwind readonly
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-ld1.ll566 ; CHECK: ld3r.8b { v0, v1, v2 }, [x0]
568 %tmp2 = call %struct.__neon_int8x8x3_t @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8* %A)
582 declare %struct.__neon_int8x8x3_t @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8*) nounwind readonly
597 ; CHECK: ld3r.16b { v0, v1, v2 }, [x0]
599 %tmp2 = call %struct.__neon_int8x16x3_t @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8* %A)
613 declare %struct.__neon_int8x16x3_t @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8*) nounwind readonly
628 ; CHECK: ld3r.4h { v0, v1, v2 }, [x0]
630 %tmp2 = call %struct.__neon_int16x4x3_t @llvm.aarch64.neon.ld3r.v4i16.p0i16(i16* %A)
644 declare %struct.__neon_int16x4x3_t @llvm.aarch64.neon.ld3r.v4i16.p0i16(i16*) nounwind readonly
659 ; CHECK: ld3r.8h { v0, v1, v2 }, [x0]
[all …]
Dfp16-vector-load-store.ll303 declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3r.v4f16.p0f16(half*)
306 declare { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3r.v8f16.p0f16(half*)
321 ; CHECK: ld3r { v0.4h, v1.4h, v2.4h }, [x0]
323 …%0 = tail call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3r.v4f16.p0f16(half* %a)
348 ; CHECK: ld3r { v0.8h, v1.8h, v2.8h }, [x0]
350 …%0 = tail call { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3r.v8f16.p0f16(half* %a)
Darm64-indexed-vector-ldst.ll2376 ;CHECK: ld3r.16b { v0, v1, v2 }, [x0], #3
2377 %ld3 = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8* %A)
2385 ;CHECK: ld3r.16b { v0, v1, v2 }, [x0], x{{[0-9]+}}
2386 %ld3 = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8* %A)
2392 declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8*) nounwind readon…
2397 ;CHECK: ld3r.8b { v0, v1, v2 }, [x0], #3
2398 %ld3 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8* %A)
2406 ;CHECK: ld3r.8b { v0, v1, v2 }, [x0], x{{[0-9]+}}
2407 %ld3 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8* %A)
2413 declare { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8*) nounwind readonly
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt1260 # CHECK: ld3r.8b { v1, v2, v3 }, [x1]
1261 # CHECK: ld3r.8b { v1, v2, v3 }, [x1], x2
1262 # CHECK: ld3r.16b { v1, v2, v3 }, [x1]
1263 # CHECK: ld3r.16b { v1, v2, v3 }, [x1], x2
1264 # CHECK: ld3r.4h { v1, v2, v3 }, [x1]
1265 # CHECK: ld3r.4h { v1, v2, v3 }, [x1], x2
1266 # CHECK: ld3r.8h { v1, v2, v3 }, [x1]
1267 # CHECK: ld3r.8h { v1, v2, v3 }, [x1], x2
1268 # CHECK: ld3r.2s { v1, v2, v3 }, [x1]
1269 # CHECK: ld3r.2s { v1, v2, v3 }, [x1], x2
[all …]
Dneon-instructions.txt2086 # CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0]
2087 # CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15]
2128 # CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3
2129 # CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15], #6
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt1260 # CHECK: ld3r.8b { v1, v2, v3 }, [x1]
1261 # CHECK: ld3r.8b { v1, v2, v3 }, [x1], x2
1262 # CHECK: ld3r.16b { v1, v2, v3 }, [x1]
1263 # CHECK: ld3r.16b { v1, v2, v3 }, [x1], x2
1264 # CHECK: ld3r.4h { v1, v2, v3 }, [x1]
1265 # CHECK: ld3r.4h { v1, v2, v3 }, [x1], x2
1266 # CHECK: ld3r.8h { v1, v2, v3 }, [x1]
1267 # CHECK: ld3r.8h { v1, v2, v3 }, [x1], x2
1268 # CHECK: ld3r.2s { v1, v2, v3 }, [x1]
1269 # CHECK: ld3r.2s { v1, v2, v3 }, [x1], x2
[all …]
Dneon-instructions.txt2086 # CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0]
2087 # CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15]
2128 # CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3
2129 # CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15], #6
/external/vixl/test/test-trace-reference/
Dlog-disasm919 0x~~~~~~~~~~~~~~~~ 4d40e018 ld3r {v24.16b, v25.16b, v26.16b}, [x0]
920 0x~~~~~~~~~~~~~~~~ 4dc2e038 ld3r {v24.16b, v25.16b, v26.16b}, [x1], x2
921 0x~~~~~~~~~~~~~~~~ 4ddfe023 ld3r {v3.16b, v4.16b, v5.16b}, [x1], #3
922 0x~~~~~~~~~~~~~~~~ 0d40ec04 ld3r {v4.1d, v5.1d, v6.1d}, [x0]
923 0x~~~~~~~~~~~~~~~~ 0dc2ec27 ld3r {v7.1d, v8.1d, v9.1d}, [x1], x2
924 0x~~~~~~~~~~~~~~~~ 0ddfec31 ld3r {v17.1d, v18.1d, v19.1d}, [x1], #24
925 0x~~~~~~~~~~~~~~~~ 4d40ec10 ld3r {v16.2d, v17.2d, v18.2d}, [x0]
926 0x~~~~~~~~~~~~~~~~ 4dc2ec34 ld3r {v20.2d, v21.2d, v22.2d}, [x1], x2
927 0x~~~~~~~~~~~~~~~~ 4ddfec2e ld3r {v14.2d, v15.2d, v16.2d}, [x1], #24
928 0x~~~~~~~~~~~~~~~~ 0d40e80a ld3r {v10.2s, v11.2s, v12.2s}, [x0]
[all …]
Dlog-disasm-colour919 0x~~~~~~~~~~~~~~~~ 4d40e018 ld3r {v24.16b, v25.16b, v26.16b}, [x0]
920 0x~~~~~~~~~~~~~~~~ 4dc2e038 ld3r {v24.16b, v25.16b, v26.16b}, [x1], x2
921 0x~~~~~~~~~~~~~~~~ 4ddfe023 ld3r {v3.16b, v4.16b, v5.16b}, [x1], #3
922 0x~~~~~~~~~~~~~~~~ 0d40ec04 ld3r {v4.1d, v5.1d, v6.1d}, [x0]
923 0x~~~~~~~~~~~~~~~~ 0dc2ec27 ld3r {v7.1d, v8.1d, v9.1d}, [x1], x2
924 0x~~~~~~~~~~~~~~~~ 0ddfec31 ld3r {v17.1d, v18.1d, v19.1d}, [x1], #24
925 0x~~~~~~~~~~~~~~~~ 4d40ec10 ld3r {v16.2d, v17.2d, v18.2d}, [x0]
926 0x~~~~~~~~~~~~~~~~ 4dc2ec34 ld3r {v20.2d, v21.2d, v22.2d}, [x1], x2
927 0x~~~~~~~~~~~~~~~~ 4ddfec2e ld3r {v14.2d, v15.2d, v16.2d}, [x1], #24
928 0x~~~~~~~~~~~~~~~~ 0d40e80a ld3r {v10.2s, v11.2s, v12.2s}, [x0]
[all …]
Dlog-cpufeatures-custom918 0x~~~~~~~~~~~~~~~~ 4d40e018 ld3r {v24.16b, v25.16b, v26.16b}, [x0] ### {NEON} ###
919 0x~~~~~~~~~~~~~~~~ 4dc2e038 ld3r {v24.16b, v25.16b, v26.16b}, [x1], x2 ### {NEON} ###
920 0x~~~~~~~~~~~~~~~~ 4ddfe023 ld3r {v3.16b, v4.16b, v5.16b}, [x1], #3 ### {NEON} ###
921 0x~~~~~~~~~~~~~~~~ 0d40ec04 ld3r {v4.1d, v5.1d, v6.1d}, [x0] ### {NEON} ###
922 0x~~~~~~~~~~~~~~~~ 0dc2ec27 ld3r {v7.1d, v8.1d, v9.1d}, [x1], x2 ### {NEON} ###
923 0x~~~~~~~~~~~~~~~~ 0ddfec31 ld3r {v17.1d, v18.1d, v19.1d}, [x1], #24 ### {NEON} ###
924 0x~~~~~~~~~~~~~~~~ 4d40ec10 ld3r {v16.2d, v17.2d, v18.2d}, [x0] ### {NEON} ###
925 0x~~~~~~~~~~~~~~~~ 4dc2ec34 ld3r {v20.2d, v21.2d, v22.2d}, [x1], x2 ### {NEON} ###
926 0x~~~~~~~~~~~~~~~~ 4ddfec2e ld3r {v14.2d, v15.2d, v16.2d}, [x1], #24 ### {NEON} ###
927 0x~~~~~~~~~~~~~~~~ 0d40e80a ld3r {v10.2s, v11.2s, v12.2s}, [x0] ### {NEON} ###
[all …]
Dlog-cpufeatures918 0x~~~~~~~~~~~~~~~~ 4d40e018 ld3r {v24.16b, v25.16b, v26.16b}, [x0] // Needs: NEON
919 0x~~~~~~~~~~~~~~~~ 4dc2e038 ld3r {v24.16b, v25.16b, v26.16b}, [x1], x2 // Needs: NEON
920 0x~~~~~~~~~~~~~~~~ 4ddfe023 ld3r {v3.16b, v4.16b, v5.16b}, [x1], #3 // Needs: NEON
921 0x~~~~~~~~~~~~~~~~ 0d40ec04 ld3r {v4.1d, v5.1d, v6.1d}, [x0] // Needs: NEON
922 0x~~~~~~~~~~~~~~~~ 0dc2ec27 ld3r {v7.1d, v8.1d, v9.1d}, [x1], x2 // Needs: NEON
923 0x~~~~~~~~~~~~~~~~ 0ddfec31 ld3r {v17.1d, v18.1d, v19.1d}, [x1], #24 // Needs: NEON
924 0x~~~~~~~~~~~~~~~~ 4d40ec10 ld3r {v16.2d, v17.2d, v18.2d}, [x0] // Needs: NEON
925 0x~~~~~~~~~~~~~~~~ 4dc2ec34 ld3r {v20.2d, v21.2d, v22.2d}, [x1], x2 // Needs: NEON
926 0x~~~~~~~~~~~~~~~~ 4ddfec2e ld3r {v14.2d, v15.2d, v16.2d}, [x1], #24 // Needs: NEON
927 0x~~~~~~~~~~~~~~~~ 0d40e80a ld3r {v10.2s, v11.2s, v12.2s}, [x0] // Needs: NEON
[all …]
Dlog-cpufeatures-colour918 0x~~~~~~~~~~~~~~~~ 4d40e018 ld3r {v24.16b, v25.16b, v26.16b}, [x0] NEON
919 0x~~~~~~~~~~~~~~~~ 4dc2e038 ld3r {v24.16b, v25.16b, v26.16b}, [x1], x2 NEON
920 0x~~~~~~~~~~~~~~~~ 4ddfe023 ld3r {v3.16b, v4.16b, v5.16b}, [x1], #3 NEON
921 0x~~~~~~~~~~~~~~~~ 0d40ec04 ld3r {v4.1d, v5.1d, v6.1d}, [x0] NEON
922 0x~~~~~~~~~~~~~~~~ 0dc2ec27 ld3r {v7.1d, v8.1d, v9.1d}, [x1], x2 NEON
923 0x~~~~~~~~~~~~~~~~ 0ddfec31 ld3r {v17.1d, v18.1d, v19.1d}, [x1], #24 NEON
924 0x~~~~~~~~~~~~~~~~ 4d40ec10 ld3r {v16.2d, v17.2d, v18.2d}, [x0] NEON
925 0x~~~~~~~~~~~~~~~~ 4dc2ec34 ld3r {v20.2d, v21.2d, v22.2d}, [x1], x2 NEON
926 0x~~~~~~~~~~~~~~~~ 4ddfec2e ld3r {v14.2d, v15.2d, v16.2d}, [x1], #24 NEON
927 0x~~~~~~~~~~~~~~~~ 0d40e80a ld3r {v10.2s, v11.2s, v12.2s}, [x0] NEON
[all …]
Dlog-all2388 0x~~~~~~~~~~~~~~~~ 4d40e018 ld3r {v24.16b, v25.16b, v26.16b}, [x0]
2392 0x~~~~~~~~~~~~~~~~ 4dc2e038 ld3r {v24.16b, v25.16b, v26.16b}, [x1], x2
2397 0x~~~~~~~~~~~~~~~~ 4ddfe023 ld3r {v3.16b, v4.16b, v5.16b}, [x1], #3
2402 0x~~~~~~~~~~~~~~~~ 0d40ec04 ld3r {v4.1d, v5.1d, v6.1d}, [x0]
2406 0x~~~~~~~~~~~~~~~~ 0dc2ec27 ld3r {v7.1d, v8.1d, v9.1d}, [x1], x2
2411 0x~~~~~~~~~~~~~~~~ 0ddfec31 ld3r {v17.1d, v18.1d, v19.1d}, [x1], #24
2416 0x~~~~~~~~~~~~~~~~ 4d40ec10 ld3r {v16.2d, v17.2d, v18.2d}, [x0]
2420 0x~~~~~~~~~~~~~~~~ 4dc2ec34 ld3r {v20.2d, v21.2d, v22.2d}, [x1], x2
2425 0x~~~~~~~~~~~~~~~~ 4ddfec2e ld3r {v14.2d, v15.2d, v16.2d}, [x1], #24
2430 0x~~~~~~~~~~~~~~~~ 0d40e80a ld3r {v10.2s, v11.2s, v12.2s}, [x0]
[all …]
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc1052 __ ld3r(v24.V16B(), v25.V16B(), v26.V16B(), MemOperand(x0)); in GenerateTestSequenceNEON() local
1053 __ ld3r(v24.V16B(), v25.V16B(), v26.V16B(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON() local
1054 __ ld3r(v3.V16B(), v4.V16B(), v5.V16B(), MemOperand(x1, 3, PostIndex)); in GenerateTestSequenceNEON() local
1055 __ ld3r(v4.V1D(), v5.V1D(), v6.V1D(), MemOperand(x0)); in GenerateTestSequenceNEON() local
1056 __ ld3r(v7.V1D(), v8.V1D(), v9.V1D(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON() local
1057 __ ld3r(v17.V1D(), v18.V1D(), v19.V1D(), MemOperand(x1, 24, PostIndex)); in GenerateTestSequenceNEON() local
1058 __ ld3r(v16.V2D(), v17.V2D(), v18.V2D(), MemOperand(x0)); in GenerateTestSequenceNEON() local
1059 __ ld3r(v20.V2D(), v21.V2D(), v22.V2D(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON() local
1060 __ ld3r(v14.V2D(), v15.V2D(), v16.V2D(), MemOperand(x1, 24, PostIndex)); in GenerateTestSequenceNEON() local
1061 __ ld3r(v10.V2S(), v11.V2S(), v12.V2S(), MemOperand(x0)); in GenerateTestSequenceNEON() local
[all …]
Dtest-cpu-features-aarch64.cc1181 TEST_NEON(ld3r_0, ld3r(v0.V8B(), v1.V8B(), v2.V8B(), MemOperand(x3)))
1182 TEST_NEON(ld3r_1, ld3r(v0.V16B(), v1.V16B(), v2.V16B(), MemOperand(x3)))
1183 TEST_NEON(ld3r_2, ld3r(v0.V4H(), v1.V4H(), v2.V4H(), MemOperand(x3)))
1184 TEST_NEON(ld3r_3, ld3r(v0.V8H(), v1.V8H(), v2.V8H(), MemOperand(x3)))
1185 TEST_NEON(ld3r_4, ld3r(v0.V2S(), v1.V2S(), v2.V2S(), MemOperand(x3)))
1186 TEST_NEON(ld3r_5, ld3r(v0.V4S(), v1.V4S(), v2.V4S(), MemOperand(x3)))
1187 TEST_NEON(ld3r_6, ld3r(v0.V1D(), v1.V1D(), v2.V1D(), MemOperand(x3)))
1188 TEST_NEON(ld3r_7, ld3r(v0.V2D(), v1.V2D(), v2.V2D(), MemOperand(x3)))
1190 ld3r(v0.V8B(), v1.V8B(), v2.V8B(), MemOperand(x3, 3, PostIndex)))
1192 ld3r(v0.V16B(), v1.V16B(), v2.V16B(), MemOperand(x3, 3, PostIndex)))
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc11858 "ld2w\003ld3\004ld3b\004ld3d\004ld3h\004ld3r\004ld3w\003ld4\004ld4b\004l"
14639 …{ 1773 /* ld3r */, AArch64::LD3Rv16b, Convert__TypedVectorList3_1681_0__Reg1_2, Feature_HasNEON, {…
14640 …{ 1773 /* ld3r */, AArch64::LD3Rv1d, Convert__TypedVectorList3_1641_0__Reg1_2, Feature_HasNEON, { …
14641 …{ 1773 /* ld3r */, AArch64::LD3Rv2d, Convert__TypedVectorList3_2641_0__Reg1_2, Feature_HasNEON, { …
14642 …{ 1773 /* ld3r */, AArch64::LD3Rv2s, Convert__TypedVectorList3_2321_0__Reg1_2, Feature_HasNEON, { …
14643 …{ 1773 /* ld3r */, AArch64::LD3Rv4h, Convert__TypedVectorList3_4161_0__Reg1_2, Feature_HasNEON, { …
14644 …{ 1773 /* ld3r */, AArch64::LD3Rv4s, Convert__TypedVectorList3_4321_0__Reg1_2, Feature_HasNEON, { …
14645 …{ 1773 /* ld3r */, AArch64::LD3Rv8b, Convert__TypedVectorList3_881_0__Reg1_2, Feature_HasNEON, { M…
14646 …{ 1773 /* ld3r */, AArch64::LD3Rv8h, Convert__TypedVectorList3_8161_0__Reg1_2, Feature_HasNEON, { …
14647 …{ 1773 /* ld3r */, AArch64::LD3Rv16b, Convert__VecListThree1281_1__Reg1_3, Feature_HasNEON, { MCK_…
[all …]

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