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/external/libunwind_llvm/src/
DUnwindRegistersRestore.S818 ldc1 $f0, (4 * 36 + 8 * 0)($4)
819 ldc1 $f2, (4 * 36 + 8 * 2)($4)
820 ldc1 $f4, (4 * 36 + 8 * 4)($4)
821 ldc1 $f6, (4 * 36 + 8 * 6)($4)
822 ldc1 $f8, (4 * 36 + 8 * 8)($4)
823 ldc1 $f10, (4 * 36 + 8 * 10)($4)
824 ldc1 $f12, (4 * 36 + 8 * 12)($4)
825 ldc1 $f14, (4 * 36 + 8 * 14)($4)
826 ldc1 $f16, (4 * 36 + 8 * 16)($4)
827 ldc1 $f18, (4 * 36 + 8 * 18)($4)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/cconv/
Dcallee-saved-float.ll63 ; O32-DAG: ldc1 [[F20]], [[OFF20]]($sp)
64 ; O32-DAG: ldc1 [[F22]], [[OFF22]]($sp)
65 ; O32-DAG: ldc1 [[F24]], [[OFF24]]($sp)
67 ; O32-DAG: ldc1 [[F26]], [[OFF26]]($sp)
69 ; O32-DAG: ldc1 [[F28]], [[OFF28]]($sp)
71 ; O32-DAG: ldc1 [[F30]], [[OFF30]]($sp)
82 ; N32-DAG: ldc1 [[F20]], [[OFF20]]($sp)
83 ; N32-DAG: ldc1 [[F22]], [[OFF22]]($sp)
84 ; N32-DAG: ldc1 [[F24]], [[OFF24]]($sp)
86 ; N32-DAG: ldc1 [[F26]], [[OFF26]]($sp)
[all …]
Dcallee-saved-fpxx.ll52 ; O32-FPXX-DAG: ldc1 [[F20]], [[OFF20]]($sp)
53 ; O32-FPXX-DAG: ldc1 [[F22]], [[OFF22]]($sp)
54 ; O32-FPXX-DAG: ldc1 [[F24]], [[OFF24]]($sp)
55 ; O32-FPXX-DAG: ldc1 [[F26]], [[OFF26]]($sp)
56 ; O32-FPXX-DAG: ldc1 [[F28]], [[OFF28]]($sp)
57 ; O32-FPXX-DAG: ldc1 [[F30]], [[OFF30]]($sp)
Dreturn-hard-float.ll45 ; O32-DAG: ldc1 $f0, %lo(double)([[R1:\$[0-9]+]])
46 ; N32-DAG: ldc1 $f0, %lo(double)([[R1:\$[0-9]+]])
47 ; N64-DAG: ldc1 $f0, %lo(double)([[R1:\$[0-9]+]])
56 ; 032FP64-DAG: ldc1 $f0, 0($sp)
57 ; 032FP64-DAG: ldc1 $f2, 8($sp)
/external/llvm/test/CodeGen/Mips/cconv/
Dcallee-saved-float.ll63 ; O32-DAG: ldc1 [[F20]], [[OFF20]]($sp)
64 ; O32-DAG: ldc1 [[F22]], [[OFF22]]($sp)
65 ; O32-DAG: ldc1 [[F24]], [[OFF24]]($sp)
67 ; O32-DAG: ldc1 [[F26]], [[OFF26]]($sp)
69 ; O32-DAG: ldc1 [[F28]], [[OFF28]]($sp)
71 ; O32-DAG: ldc1 [[F30]], [[OFF30]]($sp)
82 ; N32-DAG: ldc1 [[F20]], [[OFF20]]($sp)
83 ; N32-DAG: ldc1 [[F22]], [[OFF22]]($sp)
84 ; N32-DAG: ldc1 [[F24]], [[OFF24]]($sp)
86 ; N32-DAG: ldc1 [[F26]], [[OFF26]]($sp)
[all …]
Dcallee-saved-fpxx.ll52 ; O32-FPXX-DAG: ldc1 [[F20]], [[OFF20]]($sp)
53 ; O32-FPXX-DAG: ldc1 [[F22]], [[OFF22]]($sp)
54 ; O32-FPXX-DAG: ldc1 [[F24]], [[OFF24]]($sp)
55 ; O32-FPXX-DAG: ldc1 [[F26]], [[OFF26]]($sp)
56 ; O32-FPXX-DAG: ldc1 [[F28]], [[OFF28]]($sp)
57 ; O32-FPXX-DAG: ldc1 [[F30]], [[OFF30]]($sp)
Dreturn-hard-float.ll46 ; O32-DAG: ldc1 $f0, %lo(double)([[R1:\$[0-9]+]])
47 ; N32-DAG: ldc1 $f0, %lo(double)([[R1:\$[0-9]+]])
49 ; N64-DAG: ldc1 $f0, 0([[R1]])
58 ; 032FP64-DAG: ldc1 $f0, 0($sp)
59 ; 032FP64-DAG: ldc1 $f2, 8($sp)
/external/llvm/test/CodeGen/Mips/
Dselect.ll170 ; 32-DAG: ldc1 $[[F1:f0]], 16($sp)
175 ; 32R2-DAG: ldc1 $[[F1:f0]], 16($sp)
182 ; 32R6-DAG: ldc1 $[[F1:f[0-9]+]], 16($sp)
352 ; 32-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
353 ; 32-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
358 ; 32R2-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
359 ; 32R2-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
364 ; 32R6-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
365 ; 32R6-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
389 ; 32-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
[all …]
Dmno-ldc1-sdc1.ll13 ; Check that -mno-ldc1-sdc1 disables [sl]dc1
14 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
17 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
20 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
23 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r3 \
26 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r6 \
31 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
34 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
37 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
40 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r3 \
[all …]
Dmips64-f128-call.ll17 ; CHECK: ldc1 $f13, 8(${{[0-9]+}})
18 ; CHECK: ldc1 $f12, 0(${{[0-9]+}})
34 ; CHECK: ldc1 $f0, 0($[[R1]])
35 ; CHECK: ldc1 $f2, 8($[[R1]])
Dfp-indexed-ls.ll59 ; MIPS32R1: ldc1 $f0, 0($[[T3]])
66 ; MIPS32R6: ldc1 $f0, 0($[[T3]])
75 ; MIPS64R6: ldc1 $f0, 0($[[T3]])
142 ; MIPS32R1-DAG: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
146 ; MIPS32R2: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
149 ; MIPS32R6-DAG: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
153 ; MIPS4: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
156 ; MIPS64R6-DAG: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
Dfmadd1.ll191 ; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
197 ; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp)
203 ; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
232 ; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
238 ; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp)
244 ; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
273 ; 32-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
279 ; 32R2-NONAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
282 ; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
288 ; 32R6-DAG: ldc1 $[[T0:f[0-9]+]], 16($sp)
[all …]
Dfpxx.ll35 ; 32-FPXX: ldc1 $f0, 0($sp)
60 ; 32-FPXX: ldc1 $f0, 0($sp)
84 ; 32-FPXX: ldc1 $f0, 0($sp)
108 ; 32-FPXX: ldc1 $f0, 0($sp)
132 ; 32-FPXX: ldc1 $f0, 0($sp)
160 ; 32-FPXX: ldc1 $[[T1:f[0-9]+]], 0($sp)
163 ; 32-FPXX: ldc1 $[[T0:f[0-9]+]], 0($sp)
Do32_cc.ll8 ; ALL-DAG: ldc1 $f12, %lo
9 ; ALL-DAG: ldc1 $f14, %lo
33 ; ALL-DAG: ldc1 $f14, %lo
44 ; ALL-DAG: ldc1 $f12, %lo
70 ; ALL-DAG: ldc1 $f12, %lo
84 ; ALL-DAG: ldc1 $f12, %lo
204 ; ALL-DAG: ldc1 $f12, %lo
327 ; ALL-DAG: ldc1 $f12, %lo
339 ; ALL-DAG: ldc1 $f12, %lo
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dselect.ll233 ; 32-NEXT: ldc1 $f0, 16($sp)
241 ; 32R2-NEXT: ldc1 $f0, 16($sp)
252 ; 32R6-NEXT: ldc1 $f2, 16($sp)
497 ; 32-NEXT: ldc1 $f2, 24($sp)
498 ; 32-NEXT: ldc1 $f4, 16($sp)
506 ; 32R2-NEXT: ldc1 $f2, 24($sp)
507 ; 32R2-NEXT: ldc1 $f4, 16($sp)
514 ; 32R6-NEXT: ldc1 $f0, 24($sp)
515 ; 32R6-NEXT: ldc1 $f1, 16($sp)
553 ; 32-NEXT: ldc1 $f2, 24($sp)
[all …]
Dmno-ldc1-sdc1.ll13 ; Check that -mno-ldc1-sdc1 disables [sl]dc1
14 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
17 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
20 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \
23 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r3 \
26 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r6 \
31 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
34 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
37 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \
40 ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r3 \
[all …]
Dmips64-f128-call.ll17 ; CHECK-DAG: ldc1 $f12, %lo(gld0)(${{[0-9]+}})
18 ; CHECK-DAG: ldc1 $f13, 8(${{[0-9]+}})
37 ; CHECK: ldc1 $f0, %lo(gld1)($[[R4]])
39 ; CHECK: ldc1 $f2, 8($[[R5]])
Dfp-indexed-ls.ll59 ; MIPS32R1: ldc1 $f0, 0($[[T3]])
66 ; MIPS32R6: ldc1 $f0, 0($[[T3]])
75 ; MIPS64R6: ldc1 $f0, 0($[[T3]])
142 ; MIPS32R1-DAG: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
146 ; MIPS32R2: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
149 ; MIPS32R6-DAG: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
153 ; MIPS4: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
156 ; MIPS64R6-DAG: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
Dfpxx.ll35 ; 32-FPXX: ldc1 $f0, 0($sp)
60 ; 32-FPXX: ldc1 $f0, 0($sp)
84 ; 32-FPXX: ldc1 $f0, 0($sp)
108 ; 32-FPXX: ldc1 $f0, 0($sp)
132 ; 32-FPXX: ldc1 $f0, 0($sp)
160 ; 32-FPXX: ldc1 $[[T1:f[0-9]+]], 0($sp)
163 ; 32-FPXX: ldc1 $[[T0:f[0-9]+]], 0($sp)
Do32_cc.ll8 ; ALL-DAG: ldc1 $f12, %lo
9 ; ALL-DAG: ldc1 $f14, %lo
33 ; ALL-DAG: ldc1 $f14, %lo
44 ; ALL-DAG: ldc1 $f12, %lo
70 ; ALL-DAG: ldc1 $f12, %lo
84 ; ALL-DAG: ldc1 $f12, %lo
204 ; ALL-DAG: ldc1 $f12, %lo
327 ; ALL-DAG: ldc1 $f12, %lo
339 ; ALL-DAG: ldc1 $f12, %lo
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/llvm-ir/
Dbitcast.ll2 ; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MIPS32R2
4 ; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MIPS32FP64
6 ; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MM
8 ; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MMFP64
10 ; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MMR6
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/
Delf-relsym.s56 ldc1 $f0, %lo($CPI0_0)($2)
58 ldc1 $f2, 0($2)
60 ldc1 $f4, %lo($CPI0_1)($3)
64 ldc1 $f0, 0($1)
/external/llvm/test/MC/Mips/
Delf-relsym.s56 ldc1 $f0, %lo($CPI0_0)($2)
58 ldc1 $f2, 0($2)
60 ldc1 $f4, %lo($CPI0_1)($3)
64 ldc1 $f0, 0($1)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/Fast-ISel/
Dfpcmpa.ll143 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
144 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
163 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
164 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
183 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
184 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
203 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
204 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
223 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
224 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
[all …]
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dfpcmpa.ll143 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
144 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
163 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
164 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
183 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
184 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
203 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
204 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
223 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
224 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
[all …]

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